Global Interconnect Inductance Estimation for Accurate RLC Modeling
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Solution Overview
Problem
Current R-C analysis methods fail to accurately model inductive effects in wide interconnects of integrated circuits, leading to oversized buffers and increased inaccuracy due to the dominance of inductive effects at advanced process nodes, especially in non-symmetric clock distribution networks.
Innovation Solution
A computer-implemented method that estimates inductive effects by calculating inductance values from both parallel and non-parallel wires, incorporating a relationship between capacitance and inductance to generate a more accurate RLC model of global wires, including the effects of orthogonal structures, which were previously unaccounted for.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If R-C analysis methodology is used to model wire resistivity and electric field, then the analysis is simple and fast, but the signal propagation delay estimates are very small and non-physical, leading to incorrect conclusions
Solution Approach 1:
The patent changes the analysis parameters from purely resistive-capacitive (R-C) to include inductive effects (L). By introducing inductance as a new parameter in the RLC model, the analysis captures the electromagnetic field effects that dominate in wide interconnects at advanced process nodes, thereby obtaining physically accurate signal propagation delay estimates while maintaining computational efficiency.
Solution Approach 2:
The patent creates a composite RLC model that combines resistance, capacitance, and inductance parameters to accurately represent the complex electromagnetic behavior of wide interconnects. This composite model integrates multiple physical effects (resistive, capacitive, and inductive) into a unified analysis framework, enabling both speed and accuracy.
2Stability of the object's composition
If wide upper level interconnects are used for clock signal distribution to minimize skew, then clock distribution uniformity is improved, but inductive effects start to dominate making analysis difficult
Solution Approach 1:
The patent modifies the analysis approach by changing from R-C to RLC parameters, explicitly including inductance in the model. This parameter change enables the analysis to handle wide interconnects where inductive effects dominate, providing accurate delay estimates for clock distribution networks while maintaining the design benefits of wide wires for skew minimization.
3Ease of manufacture
If existing R-C analysis methods are used, then the analysis is straightforward, but buffers are designed to be oversized wasting area and power
Solution Approach 1:
The patent introduces inductance as a new parameter in the RLC model, which fundamentally changes the analysis results. By accounting for inductive effects, the patent obtains accurate signal propagation delays that prevent buffer oversizing, thereby reducing power consumption and area while maintaining analysis tractability through systematic RLC extraction methods.
4Device complexity
If R-C analysis is used for non-symmetric clock distribution networks, then the analysis process remains simple, but increased inaccuracy results due to asymmetry
Solution Approach 1:
The patent extends the analysis by changing from R-C to RLC parameters, enabling accurate modeling of non-symmetric clock distribution networks. The RLC model captures the electromagnetic field effects that are particularly sensitive to asymmetry, providing accurate delay estimates for non-symmetric configurations while maintaining a systematic extraction approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the accuracy of circuit designs by reducing area and power consumption while providing a more realistic model of signal propagation, addressing the limitations of prior R-C analysis methods.
Implementation Method 1
determining inductance values for parallel and non-parallel wires
Implementation Method 2
calculating capacitance values for parallel and non-parallel wires
Data Source
AI summary
Systems, methods, and other embodiments associated with analyzing interconnects for global wires of a circuit are described. In one embodiment, for a target wire in a circuit design, a method includes determining an inductance value and a capacitance value for parallel wires to the target wire. The method then calculates a second capacitance value for non-parallel wires to the target wire and calculates an estimated inductance value for the non-parallel wires based on the second capacitance value. A circuit model for the target wire may then be generated using the inductance and capacitance values.