Synchronous Clone Generation in Electronic Design Automation
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Solution Overview
Problem
Conventional electronic design methods face inefficiencies in creating and managing clones of electronic design components, particularly due to the need for manual estimation and alignment of pins/terminals, which leads to misalignment and increased computational resource usage during cloning processes.
Innovation Solution
A method and system for implementing clones in electronic designs by identifying schematic designs and applying cloning rules to generate synchronous clones without parsing the entire design, leveraging binding between schematic master cells and layout instances to determine clones based on topology and hierarchical parameters, thus conserving computational resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional top-down or bottom-up approaches are used to create electronic design cells, then design flexibility and component reusability are improved, but manual estimation and alignment of pins/terminals increases design complexity and time consumption
Solution Approach 1:
The system performs preliminary actions by automatically generating placeholder pins and terminals with estimated locations before the actual design details are available. These placeholders are created in advance at higher hierarchy levels, allowing designers to proceed with top-down design without waiting for lower hierarchy details. The placeholders are later automatically updated when actual pin locations are determined, eliminating the need for manual estimation and alignment operations.
Solution Approach 2:
The system creates copies of pin and terminal definitions across different hierarchy levels. When a pin is defined at one level, automatic cloning generates corresponding pins at parent and child hierarchy levels, ensuring consistency throughout the design. This copying mechanism eliminates manual replication efforts and ensures that all instances maintain proper connectivity relationships.
2Manufacturing precision
If manual alignment and offset of pins is performed to achieve optimal connectivity, then connection quality is improved, but the number of iterations required increases productivity loss
Solution Approach 1:
The system implements self-service by automatically performing pin alignment and connectivity optimization without requiring manual intervention. The automatic cloning mechanism inherently aligns pins between master cells and instances by copying their relative positions and connectivity relationships. The system self-corrects misalignments by automatically updating pin locations when hierarchy changes occur, eliminating the need for repeated manual alignment iterations.
Solution Approach 2:
The system establishes feedback loops that continuously monitor pin alignment and connectivity status across hierarchy levels. When misalignments are detected, the system automatically triggers corrective actions by updating placeholder pin locations. This feedback mechanism ensures that pin alignment precision is maintained without requiring manual checking and adjustment iterations, thereby preserving design productivity.
3Measurement precision
If cloning processes parse the entire electronic design to identify and create clones, then clone accuracy is improved, but computational resource usage increases significantly
Solution Approach 1:
The system segments the cloning process into targeted operations that only affect specific cells and their direct instances, rather than parsing the entire electronic design. The cloning mechanism operates locally on master cells and propagates changes only to their immediate instances, maintaining clone identification accuracy while avoiding the computational overhead of full-design parsing. This segmentation allows efficient handling of large designs with multiple independent cell instances.
Data Source
AI summary
Disclosed are methods, systems, and articles of manufacture for implementing clones for an electronic design. These methods and systems identify a schematic design of an electronic design and a set of cloning rules, configurations, or settings for implementing clones for the electronic design. These methods and systems then generate a plurality of synchronous clones in a layout of the electronic design based in part or in whole upon the set of cloning rules, configurations, or settings, without parsing the electronic design or a portion thereof.