Integrated Circuit Aging Estimation via Hierarchical Netlist Simulation
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Solution Overview
Problem
Existing methods for estimating the aging of integrated circuits (ICs) are inefficient and lack accuracy, leading to potential reliability issues and increased time-to-market due to complex calculations and errors associated with flattened netlists.
Innovation Solution
A method and system that utilize a process design kit (PDK) with embedded measurement commands to perform circuit simulations, allowing for direct calculation of aging parameters without flattening the netlist, thereby reducing complexity and improving estimation accuracy and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing methods for estimating IC aging are used, then aging estimation can be performed, but the process is inefficient and lacks accuracy due to complex calculations and errors associated with flattened netlists
Solution Approach 1:
The invention extracts and removes the problematic flattened netlist step from the aging estimation process. Instead of flattening the netlist, the method directly uses the original hierarchical netlist structure, eliminating the source of errors and complexity while maintaining estimation accuracy.
Solution Approach 2:
The invention segments the aging estimation process into distinct phases: obtaining the netlist, extracting aging parameters directly from the hierarchical structure, and performing calculations. This segmentation avoids the need for netlist flattening and enables parallel processing of different circuit components, improving efficiency.
2Loss of information
If netlist flattening is performed to extract aging parameters, then parameter extraction can be achieved, but device complexity and error potential increase significantly
Solution Approach 1:
The invention extracts aging parameters directly from the hierarchical netlist structure without performing flattening. This extraction approach maintains the original circuit hierarchy and relationships while obtaining all necessary aging parameters, eliminating the complexity and error risks associated with netlist flattening.
3Reliability
If complex calculation methods are used for aging estimation, then comprehensive aging data can be obtained, but re-design time and time-to-market increase
Solution Approach 1:
The invention performs preliminary extraction of aging parameters directly from the netlist before detailed aging calculations. By preparing the parameter extraction in advance using the hierarchical structure, the method reduces the time required for subsequent aging analysis and minimizes re-design cycles.
Solution Approach 2:
The invention changes the approach from complex iterative calculations on flattened netlists to direct parameter extraction and simplified calculations on hierarchical netlists. This parameter change in the methodology reduces computational complexity while maintaining comprehensive aging assessment for improved IC reliability.
Data Source
AI summary
A method of estimating aging of an integrated circuit (IC) includes: obtaining a first process design kit (PDK) including a plurality of first device models corresponding to a plurality of devices provided by a process of fabricating the IC; obtaining values of aging parameters of device instances included in a netlist defining the IC, by performing a first circuit simulation based on the netlist and the first PDK; and obtaining aging data of the IC by performing a second circuit simulation based on the values of the aging parameters and the netlist, wherein each of the plurality of first device models includes at least one measurement command to be executed in the first circuit simulation to calculate an aging parameter.