Buffer Allocation Guidance in Multicore Architectures
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Solution Overview
Problem
In multicore circuit architectures, existing methods for compiling designs fail to efficiently allocate buffers based on dataflows, leading to potential deadlock conditions and suboptimal execution performance due to inadequate handling of buffer dependencies.
Innovation Solution
A method is introduced that converts a design from a high-level programming language into an intermediate representation, performs data flow dependence analysis to determine buffer dependencies, and generates buffer constraints to guide the allocation of buffers across compute tiles and memory banks, thereby optimizing buffer mapping to reduce inter-core communication and enhance parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If buffers are allocated without dataflow-based dependency analysis, then compilation is simpler and faster, but deadlock conditions may occur and execution performance deteriorates
Solution Approach 1:
The patent performs buffer dependency analysis during the compilation phase before execution, identifying and recording buffer dependencies in advance. This preliminary action ensures that buffers are allocated in a deadlock-free manner without requiring complex runtime checks, thus improving reliability while keeping the compilation process manageable.
Solution Approach 2:
The patent introduces an intermediate representation (IR) as a mediator between the high-level design and the multicore architecture. The buffer dependency analysis is performed on this IR, which simplifies the complexity by providing a standardized intermediate form to analyze, rather than directly analyzing the complex hardware architecture or high-level code.
2Productivity
If buffers are allocated without considering dataflow dependencies, then buffer allocation is faster and simpler, but inter-core communication increases and parallelism is reduced
Solution Approach 1:
The patent performs buffer dependency analysis and generates buffer constraints during compilation, before execution. This preliminary analysis identifies which buffers can be safely allocated to different compute tiles to maximize parallelism, enabling faster execution without requiring complex runtime dependency checks.
Solution Approach 2:
The patent changes the allocation parameters of buffers based on dependency analysis results. Independent buffers are allocated to different compute tiles or memory banks to enable parallel access and reduce inter-core communication, while dependent buffers are kept together. This parameter optimization improves execution speed without requiring complex runtime mechanisms.
3Productivity
If buffer constraints are generated through dataflow analysis, then buffer mapping is optimized for parallelism, but compilation time increases
Solution Approach 1:
The patent performs buffer dependency analysis on the intermediate representation, which is a simplified version of the full program. By analyzing only the critical dataflow paths in the IR rather than the entire program in full detail, the patent achieves sufficient parallelism optimization with acceptable compilation time overhead.
Solution Approach 2:
The patent optimizes buffer allocation parameters (compute tile assignment, memory bank assignment) based on dependency analysis. By focusing on changing these critical allocation parameters rather than optimizing all aspects of the compilation, the patent achieves improved parallel execution efficiency with minimal impact on compilation time.
Data Source
AI summary
Providing dataflow based guidance for buffer allocation in a multicore circuit architecture includes converting, using computer hardware, an application specified in a high-level programming language into an intermediate representation. Buffers of dataflows of the intermediate representation are detected. Determining whether the buffers are independent or dependent based on an analysis of the dataflows of the intermediate representation. Buffer constraints are generated. The buffer constraints specify whether the buffers are independent and dictate a mapping of the buffers in the multicore circuit architecture.