Integrated Circuit Power Optimization via Graph-Based Move Selection
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Solution Overview
Problem
Current integrated circuit design methods face challenges in optimizing power consumption while maintaining speed constraints, particularly due to excessive leakage current as devices shrink, and existing methodologies struggle to effectively incorporate multiple design variables for optimal power-performance trade-offs.
Innovation Solution
The method involves a graph-based approach that performs concurrent optimization of integrated circuits by assigning discrete operations such as threshold voltage, device length, and power supply adjustments, converting a timing graph into a move graph to identify power-saving modifications without violating timing constraints, using a graph-based engine that evaluates changes concurrently under given constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If devices are shrunk to increase speed, then speed is improved, but leakage current increases causing excessive power consumption
Solution Approach 1:
The patent applies different threshold voltages to different transistors based on their specific functional requirements and timing constraints. Critical path transistors use lower Vt for speed, while non-critical transistors use higher Vt to reduce leakage, creating local quality variations in the circuit
Solution Approach 2:
The patent changes the threshold voltage parameter of transistors from a single uniform value to multiple discrete values (e.g., low-Vt, standard-Vt, high-Vt) to optimize the trade-off between speed and power consumption in different circuit regions
2Speed
If transistor width is continuously tuned for timing optimization, then timing performance is improved, but power consumption increases and runtime increases
Solution Approach 1:
The patent segments the continuous transistor width adjustment into discrete sizing categories (e.g., 0.5x, 0.75x, 1.0x, 1.25x, 1.5x of original width). This discretization allows the optimizer to explore fewer configurations while still achieving effective timing and power optimization
Solution Approach 2:
The patent dynamically adjusts transistor width based on timing constraints and power objectives, using an iterative optimization process that modifies widths selectively rather than uniformly across the circuit
3Loss of energy
If multiple design variables are simultaneously optimized, then power-performance trade-off is improved, but computational complexity and runtime increase
Solution Approach 1:
The patent segments the optimization problem into discrete variables (threshold voltage assignment, gate sizing, channel length adjustment) that can be independently controlled and optimized, reducing the continuous search space to discrete options
Solution Approach 2:
The patent merges multiple optimization operations (Vt assignment, gate sizing, channel length biasing) into a unified optimization framework that simultaneously considers all variables, achieving better power-performance trade-offs than sequential optimization
4Loss of energy
If discrete operations are performed on circuit components for power reduction, then power consumption is reduced, but timing constraints may be violated
Solution Approach 1:
The patent uses timing analysis feedback to guide the discrete optimization operations. After each modification (Vt change, gate sizing), the timing impact is evaluated and fed back to adjust subsequent optimization steps, ensuring timing constraints are maintained
Solution Approach 2:
The patent applies discrete operations partially - not all transistors are modified, but only those where the power savings outweigh the timing impact. The optimization selectively applies Vt changes and sizing adjustments to specific circuit regions
Data Source
AI summary
A graph-based iterative method is provided for selecting component modifications in an integrated circuit design that reduce the power consumption to a minimum while still meeting timing constraints. Channel-connected components are represented as nodes in a timing graph and edges in the timing graph represent directed paths. From the timing graph, a move graph is constructed containing a plurality of move nodes. Each move node represents a change to one of the components in one of the timing graph nodes. A given timing graph node can result in a plurality of move nodes. Move nodes can be merged into group nodes, and both the move nodes and group nodes are assigned a weight based on the change in power and timing effects of the associated components changes. These weights are used to select move nodes or group nodes. In general, a set of move or group nodes is selected representing the maximum cumulative weight and the components changes associated with the nodes in the set are performed on the integrated circuit design. Moves that cause timing violations are reversed. The node weights are updated following components changes and the selection of node sets is repeated iteratively until the power consumption converges to a minimum.