Analog Delay Line Adaptive Biasing for Low-Voltage DLL Lock Range
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Solution Overview
Problem
As electronic devices increase in speed, timing requirements for delay locked loops (DLLs) are also increasing, but voltage regulators become infeasible at lower power supply voltages, and analog delay elements consume excessive power and area.
Innovation Solution
Implementing an analog delay line with adaptive biasing techniques and shared bias circuits, reducing power and area consumption while improving the lock range, and using digital control signals with analog delay elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If voltage regulators are used to maintain constant power supply voltage and reduce jitter or skew, then timing stability is improved, but device complexity and area increase
Solution Approach 1:
The patent removes voltage regulators from the DLL circuit by using intrinsically low-voltage delay elements that operate directly at lower power supply voltages without requiring external voltage regulation, thereby reducing device complexity while maintaining timing stability through the inherent characteristics of the delay elements
Solution Approach 2:
The delay elements are designed to self-adjust and maintain proper timing characteristics at lower voltages through their intrinsic properties, eliminating the need for external voltage regulators and allowing the circuit to serve itself without additional complexity
2Measurement precision
If analog delay elements are used in DLLs, then timing precision is improved, but power consumption and area increase
Solution Approach 1:
The patent changes the operating parameters of the delay elements by designing them to operate intrinsically at lower power supply voltages (e.g., 1.2V or lower), which reduces power consumption while maintaining the analog timing precision needed for DLL operation
Solution Approach 2:
The delay line is divided into multiple discrete delay elements that can be individually controlled and optimized, allowing for precise timing control with reduced power consumption compared to traditional monolithic analog delay lines
3Device complexity
If traditional delay elements are used, then circuit simplicity is maintained, but lock range is insufficient for high-speed operation
Solution Approach 1:
The patent implements dynamic control of the delay elements through digital control signals that can adjust the delay amount in real-time, enabling the DLL to achieve a wide lock range for high-speed operation while maintaining relatively simple circuit architecture
Solution Approach 2:
The delay elements are designed to perform multiple functions: they provide precise timing delay, operate at low voltages, and can be dynamically controlled over a wide range, making them universally applicable to high-speed DLL operations without requiring complex specialized circuits
Data Source
AI summary
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.