Pulse Automatic Control TRIZ Cases

Dual feedback loops adjust delay stages and duty ratio together, suppressing phase shifts in multi-phase clock outputs while reducing correction hardware.

A well transient detector and masking circuit suppress output-voltage noise in single-end level shifters for reliable floating gate drivers.

Uses one feedback clock with edge selection and differential phase processing to cut circuit area, power, and phase-tracking interference.

A divided feedback clock path uses lower-frequency phase detection to cut power and propagation delay while preserving duty-cycle correction.

Frequency-based supply control lets a memory DLL delay line keep accurate timing across a wider operating range without adding delay elements.

A PMOS-capacitor pull-up path keeps node voltage valid during negative supply startup, ensuring reliable power-on reset output.

Programmable transconductors steer phased tank currents so an LC oscillator holds a temperature-null phase and reduces frequency drift and jitter.

Adjustable capacitance lets injection-locked dividers calibrate to target frequency, widening PLL lock range while cutting power and phase noise.

Compensation circuits let one input stage handle differential and single-ended signals with lower power, less skew, and no multiplexer.

A master-slave digital DLL uses differential-delay cells and averaging to cut area and power while resisting duty-cycle variation and jitter.

Adaptive biasing lets analog delay lines start up and lock over a wider range while cutting DLL power and area at low supply voltage.

Asynchronous reset and clock gating force mux/demux divider chains into a known state, preserving bit alignment while easing power and test issues.

A control signal and coupling circuit let a level converter handle power supply sequencing while minimizing through currents and LSI power use.

Current-steered biasing lets an analog phase interpolator run at low supply voltage while preserving clock alignment in CDR circuits.

Dynamic loop bandwidth adjustment improves Doppler and phase tracking at low SNR, reducing noise impact and bit error rate.

Stored PLL control voltage lets the VCO restart near its prior state, cutting lock re-acquisition time after STOP mode.

Current-mirror control lets a level shifter match transistor current, reducing layout area and power use across different voltage ranges.

Parallel PMOS-NMOS trimming switches with dummy NMOS devices cut leakage and preserve linearity for accurate internal clock trimming.

Active or passive analog differentiators modulate clock frequency to reduce EMI while avoiding the complexity and power draw of digital circuitry.

By switching between divided and direct clock comparison by control period, this circuit stabilizes phase detection under jitter and noise.

A feedback circuit compares actual and target LO voltage levels to correct duty cycle, improving RF receiver linearity and noise figure.

A level-shifting capacitor keeps Vgs nearly constant in a sampling switch, cutting distortion across the input range with lower amplifier overhead.

Quadrature clocking and a cascaded bi-stable chain cut critical path delay and spurious tones in non-integer frequency division.

Periodic switching resets choke flux so wideband DC differential signals can cross large common-mode voltages without saturation or fidelity loss.

A monotonic voltage-to-current control circuit widens oscillator tuning range, cuts jitter, and enables smaller PLL filter capacitors.

A resistor-set strobe phase advance and receiver delay equalization compensate bus skew, improving source-synchronous data integrity and throughput.

A dual-polyhedral oscillator array combines inertial sensing and clock averaging to keep navigation and timing stable when GPS or TPS is lost.

A charge-pump edge density detector compares reference and feedback edge rates to generate phase-independent control voltage for frequency lock loops.

Phase and frequency tracking accelerators compensate loop filter delay in timing recovery, improving loop bandwidth and jitter tolerance.

Using phase interpolation and phase rotation control, this circuit tunes a fixed crystal reference to match input clock frequency with low jitter.

A switch circuit lifts the output transistor bulk in tri-state mode, letting the buffer withstand external high voltage without losing active-mode operation.

Lightly doped PMOS transistors absorb high voltage stress, enabling voltage switch circuits to use standard logic fabrication with lower complexity and cost.

Cycle-count-based offset correction restores phase coherence in fractional-N PLL signals after loss of lock, supporting GNSS baseband processing.

Adaptive digital and analog phase detection widens the lock window and lowers detection frequency to keep DLL clocks stable under jitter and noise.

A slave-side PLL locks to a predefined CAN frame bit pattern to recover bus clock timing, cutting crystal count, cost, and power use.

Three-stage PLL VCO calibration shortens TDD transmit-receive switching while keeping frequency alignment locked to the reference signal.

A delay-controlled PLL synthesizer replaces frequent divider-ratio changes to reduce jitter noise, speed locking, and avoid larger loop-filter capacitors.

Selectable feedback in a delay line adjusts clock frequency while preserving 50% duty cycle and avoiding added PLL size and interference.

Bias tuning of PMOS and NMOS gate voltages matches differential rise and fall times, cutting common-mode noise and EMI.

A delay unit enables odd integer clock division while preserving 50% duty cycle, maximum input frequency, and low power and area.

Continuous video clock adjustment removes audio-video drift and avoids frame-drop artifacts for stable synchronized playback.

Dynamic clock frequency tracks process, voltage, and temperature shifts so digital circuits run near their workable limit with stable power use.

A clamp circuit fixes capacitor potential to stop MOS gate floating, preserving waveform shape and signal integrity when power is off.

Phase-shift sampling and logic-state counting measure clock duty cycle accurately in-circuit without costly oscilloscopes or manual probing.

A fast calibrated oscillator samples a slower clock at power-on to cut factory test cost while maintaining accurate frequency adjustment.

Multiple phase signals split the detection window in a digital delay locked loop, cutting static phase offset and reducing PVT sensitivity.

A VCO-based DLL replaces tap delay lines to generate integer-multiplied clocks with lower noise, fewer spurs, and reduced duty-cycle distortion.

A minimal adder-multiplier-register circuit generates flexible poly-phase sync sequences faster while avoiding costly buffers and squaring.

A flip-flop delay chain holds off external clock edges for two cycles after reset, preventing timing violations and simplifying testing.

Separate power-down control lets internal circuits sleep during DLL locking, cutting current while preserving internal clock stability.