Mixed-Mode DLL Phase Detection for Noise-Resistant Lock Hold
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Solution Overview
Problem
Existing Delay-Locked Loop (DLL) circuits in high-speed digital systems face challenges in maintaining a locked state due to jitter and noise, leading to frequent unlocking and increased jitter performance issues in noisy environments.
Innovation Solution
The implementation of a mixed-mode DLL circuit with adaptive digital and analog phase detection, featuring a digital phase detector and an analog phase detector that adjusts the phase detection window and frequency to maintain lock conditions, ensuring robust phase alignment and reduced jitter through adaptive configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed narrow phase detection window is used in DLL circuits, then the circuit can achieve fast locking, but it cannot maintain lock state under jitter and noise conditions
Solution Approach 1:
The patent implements dynamic adjustment of the phase detection window width based on lock state detection. When locked, the window is narrowed to improve jitter performance; when unlocked or in noise conditions, the window is widened to maintain reliable lock detection. This dynamic adaptation resolves the contradiction between fast locking and reliable lock maintenance under varying conditions.
Solution Approach 2:
The system changes the parameter of phase detection window width adaptively based on operating conditions. By monitoring lock state and adjusting the window width parameter, the system achieves both fast initial locking (wider window) and stable maintained locking (narrower window), resolving the contradiction between speed and reliability.
2Speed
If the phase detection frequency is kept high, then the locking speed is fast, but the jitter performance deteriorates in noisy environments
Solution Approach 1:
The patent dynamically adjusts the phase detection frequency based on the lock state. During initial acquisition, a higher frequency enables fast locking. Once locked, the frequency is reduced to improve jitter performance and noise rejection. This dynamic frequency adjustment resolves the contradiction between fast locking and stable jitter performance.
Solution Approach 2:
The system employs periodic phase detection at different frequencies depending on the operational phase. High-frequency periodic detection is used during acquisition, transitioning to lower-frequency periodic detection during maintained lock, optimizing both speed and stability at different stages.
3Reliability
If a simple phase detection circuit is used, then the device complexity is low, but the ability to maintain lock under noise conditions is insufficient
Solution Approach 1:
The patent implements feedback mechanisms where the phase detector output is monitored to detect lock state and noise conditions. This feedback is used to adaptively adjust the phase detection window and frequency, enabling the circuit to maintain lock under noise conditions without requiring a completely complex circuit architecture.
Solution Approach 2:
The phase detection circuit performs self-adjustment based on its own output characteristics. By monitoring its own lock detection signals and adapting its parameters accordingly, the circuit achieves noise immunity through self-service rather than requiring external complex control systems.
Data Source
AI summary
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.