Power-On Reset Circuit for Negative Supply Startup
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Solution Overview
Problem
Conventional power-on reset circuits for CMOS semiconductor integrated circuits fail to operate normally when internal voltage becomes unstable, particularly when the power supply voltage rises from a negative state, leading to failure in outputting a power-on reset signal.
Innovation Solution
A power-on reset circuit comprising a NMOS transistor, a depletion-type NMOS transistor, a PMOS transistor, a capacitor, and a waveform shaping circuit, where the PMOS transistor turns ON when a sufficient potential difference exists between power supply terminals, charging the capacitor and ensuring output of a power-on reset signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power supply voltage rises from a negative state, then the circuit should initialize properly, but the node C voltage falls below ground voltage causing the waveform shaping circuit to fail
Solution Approach 1:
The patent introduces a pull-up element connected to node C that acts as an intermediary to counteract the negative voltage effect. This pull-up element ensures that even when node C voltage tends to fall below ground due to negative power supply conditions, the voltage is pulled back to a valid level, allowing the waveform shaping circuit to function properly and output the reset signal.
Solution Approach 2:
The patent applies preliminary anti-action by incorporating the pull-up element that proactively counteracts the potential harmful effect of negative voltage on node C before it can prevent the reset signal output. This preliminary protective action ensures the circuit can handle power supply variations including negative voltage conditions.
2Stability of the object's composition
If a pull-down element is added at node C to stabilize voltage, then voltage stability improves, but the circuit cannot handle power supply rising from negative state
Solution Approach 1:
The patent merges both pull-up and pull-down elements at node C, combining their opposing functions to achieve both voltage stability and adaptability. The pull-down element provides stability during normal operation, while the pull-up element ensures the circuit can handle power supply rising from negative states, creating a robust voltage control mechanism that satisfies both requirements simultaneously.
3Use of energy by moving object
If the waveform shaping circuit is activated after power supply stabilization, then power consumption is reduced, but the reset signal cannot be output when power supply rises from negative state
Solution Approach 1:
The patent applies preliminary action by ensuring the pull-up element is in place and functional before the waveform shaping circuit is activated. This preliminary preparation ensures that when the power supply rises from a negative state, node C voltage is already protected, allowing the waveform shaping circuit to successfully output the reset signal once activated, thus maintaining reliability without excessive power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures the output of a power-on reset signal regardless of the power supply activation state, maintaining circuit initialization across varying power supply conditions.
Implementation Method 1
a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal
Implementation Method 2
When there is a sufficient potential difference between the power supply terminals, the PMOS transistor turns ON so as to charge the capacitor
Implementation Method 3
electrical charge stored in the capacitor 111 is discharged through a depletion-type NMOS transistor 101
Data Source
AI summary
The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output.