PLL Control Voltage Storage for Fast Lock Re-Acquisition
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Solution Overview
Problem
Phase-locked loop (PLL) circuits in integrated circuits experience a long lock re-acquisition time when transitioning from a STOP mode to a RUN mode, which increases wake-up time and is undesirable for time-critical applications.
Innovation Solution
Incorporating a voltage storage circuit with a unity-gain amplifier and switches to sample and store control voltage during the RUN mode, and then provide it during the transition to the STOP mode, allowing the PLL to quickly re-acquire lock when switching back to the RUN mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the PLL is switched OFF during STOP mode to save power, then power consumption is reduced, but the lock re-acquisition time increases when transitioning back to RUN mode
Solution Approach 1:
The invention performs preliminary action by storing the control voltage value before the PLL is switched OFF during STOP mode. When transitioning back to RUN mode, this pre-stored voltage is immediately provided to the VCO, eliminating the need for the PLL to re-acquire lock from scratch. This resolves the contradiction by preparing the system in advance (storing voltage) so that the time penalty for switching OFF can be avoided during wake-up.
2Loss of time
If the PLL remains ON during STOP mode to maintain lock, then lock re-acquisition time is reduced, but power consumption increases
Solution Approach 1:
The invention extracts and stores only the essential parameter (control voltage) needed for PLL operation before shutdown. This allows the PLL to be completely switched OFF during STOP mode (saving power) while retaining the critical information needed for rapid re-acquisition. The control voltage is extracted from the LPF output and stored in a voltage storage circuit, separating the power-consuming active components from the essential operational parameter.
3Stability of the object's composition
If the control voltage is continuously provided to the VCO during mode transitions, then frequency stability is maintained, but the wake-up time increases due to PLL settling requirements
Solution Approach 1:
The control voltage is sampled and stored in advance before the mode transition occurs. When waking up from STOP mode, this pre-stored voltage is immediately supplied to the VCO, providing frequency stability from the very beginning of the transition rather than requiring the PLL to settle after startup. This preliminary preparation eliminates the settling time requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the PLL lock re-acquisition time, enhancing the wake-up performance and efficiency of integrated circuits by enabling faster transition from STOP to RUN mode.
Implementation Method 1
Incorporating a voltage storage circuit with a unity-gain amplifier and switches to sample and store control voltage during the RUN mode, and then provide it during the transition to the STOP mode
Data Source
AI summary
A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.