CAN Bus Clock Recovery Using PLL-Synced Bit Patterns
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Solution Overview
Problem
The high cost of evaluation electronics for CAN bus systems, particularly due to the requirement of oscillating crystals or quartz for accurate operation, makes ceramic resonators insufficient and costly alternatives.
Innovation Solution
A method where a master device with a clock generator provides a clock frequency to slave devices via a CAN bus, using a phase-locked loop with a predetermined bit pattern to recover the clock frequency without the need for ceramic resonators or quartz oscillators, allowing for cost-effective and simple clock recovery in slave devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If oscillating crystals or quartz are used in slave devices for accurate CAN operation, then measurement precision is improved, but device complexity and cost increase
Solution Approach 1:
The clock generation function is extracted from slave devices and centralized in the master device. The master device generates the clock frequency and transmits it through the CAN bus, while slave devices only need to receive and synchronize to this external clock signal, eliminating the need for independent crystal oscillators in each slave device.
Solution Approach 2:
The CAN bus itself serves as an intermediary carrier for clock synchronization. Instead of each device having its own independent clock source, the clock signal is transmitted through the CAN bus medium, and slave devices use phase-locked loops to synchronize their internal clocks to the master device's clock through this intermediary channel.
2Device complexity
If ceramic resonators are used instead of oscillating crystals, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The invention allows slave devices to use simpler, less expensive clock components (such as ceramic resonators or even RC oscillators) since they do not need to generate high-precision clock signals independently. Instead, they synchronize to the master device's precise clock through the CAN bus, making the slave devices' clock components expendable in terms of precision requirements.
3Reliability
If each slave device has independent clock generation, then reliability is improved, but device complexity increases
Solution Approach 1:
The phase-locked loop in each slave device provides feedback control to synchronize the slave's internal clock with the master device's clock signal received through the CAN bus. The PLL continuously adjusts the slave clock frequency and phase based on the received synchronization bits, ensuring reliable clock synchronization without independent high-precision clock generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of crystals required in a CAN bus system, enabling flexible data transmission rate adjustments and power consumption reduction, primarily by modifying the master device, while maintaining accurate clock synchronization.
Implementation Method 1
providing the slave device with a phase locked loop; and operating the phase-locked loop with the extracted, predetermined bit pattern as a reference signal for recovering the clock frequency
Data Source
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AI summary
The present invention proposes a method, a CAN bus driver, and a CAN bus system for recovering a clock frequency of a CAN bus, said CAN bus comprising a master device having a clock frequency generator for producing the clock frequency, the master device being coupled to a slave device. A phase-locked loop is used in the slave device, the phase-locked loop using a prespecified bit patten as reference signal, and the bit pattern is extracted from the frames transmitted by the master device via the bus system.