PLL Frequency Synthesizer Using Delay Control to Cut Jitter
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional sigma-delta modulating frequency synthesizers suffer from high jitter noise due to significant variations in frequency dividing ratios, leading to slower phase locking and increased manufacturing costs, as they require larger capacitors for filtering noise, which in turn slows reaction speed and increases chip area.
Innovation Solution
A frequency synthesizer with a delay unit, phase-locked loop, and control unit that generates a delay parameter and frequency dividing parameter based on a target magnification factor, allowing for fractional-number frequency division with reduced jitter noise by adjusting the delay unit and frequency divider operations, thereby minimizing the need for frequent changes in frequency dividing ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sigma-delta modulator controls frequency divider to perform frequency dividing procedure of 5 times and 6 times for acquiring output signal with average frequency equaling 5.3 times reference frequency, then required output frequency is achieved, but signal variation margin reaches 20% which results in significant jitter noise
Solution Approach 1:
The patent changes the control parameter from frequency dividing ratio to delay time. Instead of varying the frequency dividing ratio between 5 and 6 to achieve 5.3 times multiplication, the invention maintains a fixed frequency dividing ratio and uses delay time adjustment to achieve the same frequency synthesis goal, thereby eliminating the 20% signal variation and reducing jitter noise
Solution Approach 2:
The patent replaces the mechanical frequency switching mechanism (changing frequency dividing ratios) with a time-delay mechanism. The delay unit introduces a controlled time delay to the reference signal, allowing the phase-locked loop to achieve the desired frequency multiplication without varying the frequency dividing ratio, thus eliminating jitter noise
2Productivity
If phase-locked loop uses sigma-delta modulating structure for frequency synthesizing, then frequency multiplication is achieved, but speed of phase locking may be slow if accuracy of frequency divider is insufficient
Solution Approach 1:
The patent changes the controlling parameter from frequency dividing ratio to delay time. By using delay time as the control variable instead of frequency dividing ratio, the system achieves faster phase locking without requiring high-precision frequency dividers, as the delay unit can be implemented with simpler circuitry
3Object-generated harmful factors
If greater capacitor is configured for filtering jitter noise in phase-locked loop, then jitter noise is reduced, but reaction speed becomes slower and area of integrated chip increases leading to increased manufacture cost
Solution Approach 1:
The patent converts the harmful jitter noise generated by frequency dividing ratio variations into a beneficial solution by eliminating the source of the noise. Instead of adding filtering components (capacitors) to remove the noise, the invention redesigns the frequency synthesis mechanism to prevent jitter noise generation in the first place, thereby maintaining fast reaction speed and small chip area
Data Source
AI summary
The present invention discloses a frequency synthesizer. The frequency synthesizer includes a delay unit, for receiving a reference signal and delaying the reference signal according to a delay parameter, so as to generate a delay reference signal; a phase-locked loop, for generating an output signal according to the delay reference signal and a feedback frequency dividing signal; a control unit, for generating the delay parameter and a frequency dividing parameter according to a target magnification factor; and a frequency divider, for dividing the frequency of the output signal according to the frequency dividing parameter.