Memory DLL Delay Line with Variable Supply for Wide Frequency Range
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Solution Overview
Problem
Conventional DLL systems in memory devices are limited by their fixed power supply, which restricts their operating frequency range, leading to inaccurate data output when operating outside standard frequencies, and disabling the DLL system is not a viable solution as it affects memory accuracy.
Innovation Solution
A DLL system with a modulated power supply that dynamically adjusts based on the operating frequency, using a frequency detection mechanism and control logic to generate logic signals that adjust the power supply to the delay line, allowing the DLL to function accurately at frequencies outside its prescribed range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of delay elements within the DLL is increased to extend the operating frequency range, then the frequency application range is improved, but the area occupied by the DLL delay line increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the power supply voltage to the delay line based on the operating frequency. A voltage regulator modifies the power supply parameter according to detected frequency ranges, allowing the same delay line to achieve different delay characteristics without physical modification. This resolves the contradiction by extending frequency adaptability through electrical parameter modulation rather than increasing the number of delay elements.
2Use of energy by moving object
If the DLL system is disabled during low frequency operation to save power, then energy consumption is reduced, but the accuracy of data output timing is adversely affected
Solution Approach 1:
The patent implements dynamics by making the power supply to the delay line dynamically adjustable rather than fixed. The system continuously monitors operating frequency and adjusts the power supply voltage accordingly using a voltage regulator. This allows the DLL to remain operational across wide frequency ranges while optimizing power consumption, eliminating the need to disable the DLL at low frequencies and thereby maintaining timing accuracy.
Solution Approach 2:
The patent changes the power supply parameter dynamically based on operating conditions. By detecting the current frequency range and adjusting the power supply voltage through a regulator, the system optimizes power consumption at different frequencies while maintaining proper delay characteristics and timing accuracy, resolving the contradiction between energy saving and precision.
3Adaptability or versatility
If the power supply to the delay line is fixed, then the device complexity is reduced, but the operating frequency range is limited
Solution Approach 1:
The patent introduces a voltage regulator as an intermediary component between the fixed power source and the delay line. This mediator dynamically adjusts the power supply voltage based on frequency detection, enabling extended frequency operation without directly modifying the delay line structure. The added complexity is localized to the control circuitry while the core delay line remains simple.
Data Source
AI summary
A DLL system in a memory device with wide frequency application includes: a clock receiver that generates a clock for the DLL system; a delay line, coupled to the clock receiver, for receiving the generated clock and delaying the clock according to a received power supply; a power regulator, for generating the power supply to the DLL delay line according to a bias; a control logic, coupled to the clock receiver, for generating a plurality of logic signals respectively corresponding to a plurality of frequency ranges of the clock; and a bias generator, coupled between the control logic and the power regulator, for providing the bias to the power regulator, wherein the value of the bias is according to a logic signal output by the control logic.