VCO-Based DLL Frequency Multiplier With Low Noise and Spur Control
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) used for frequency multiplication suffer from noise and spurs in the output clock signal, and programmability of the multiplying factor is difficult to implement, making them inefficient for precise frequency multiplication.
Innovation Solution
A DLL design that employs a voltage-controlled oscillator (VCO) instead of tap-controlled delay lines, allowing for frequency multiplication by an integer multiple while minimizing noise and spurs, using a phase detector, charge pump, and synchronization logic to adjust the control voltage and align the phases of the input and output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If tap-controlled delay lines are used for frequency multiplication, then the DLL can generate multiple phase delays, but noise and spurs are introduced in the output clock signal
Solution Approach 1:
The patent extracts and removes the problematic tap-controlled delay line portion from the frequency multiplication path. Instead of using multiple delay taps that generate noise and spurs, the invention uses a single delay element controlled by a digitally controlled oscillator (DCO) to achieve frequency multiplication without the harmful side effects of traditional delay line-based multiplication.
Solution Approach 2:
The patent replaces the mechanical/analog delay line structure with a digitally controlled oscillator approach. The DCO generates the multiplied frequency signal through digital control mechanisms rather than analog delay propagation, thereby eliminating the noise and spurs inherent in analog delay line operations while maintaining the frequency multiplication function.
2Adaptability or versatility
If conventional DLLs are used for frequency multiplication, then the circuit can generate multiple clock phases, but the circuit area increases and programmability is difficult
Solution Approach 1:
The patent implements a universal frequency multiplication architecture where the DCO can be programmed to generate any integer multiple of the input frequency through digital control. This single multi-functional block replaces what would traditionally require multiple specialized delay lines or oscillators, significantly reducing circuit area while maintaining full frequency multiplication capability.
Solution Approach 2:
The patent introduces dynamic programmability through the DCO, which can be reconfigured via digital control signals to multiply the input frequency by different integer factors. This dynamic adjustment capability eliminates the need for fixed, hardwired multiplication circuits, reducing circuit area while enabling flexible and programmable frequency synthesis.
3Manufacturing precision
If tap-controlled delay lines are used, then frequency multiplication can be achieved, but duty cycle errors and distortion are introduced
Solution Approach 1:
The patent replaces the analog delay line mechanism with a digitally controlled oscillator that generates clean, synchronized clock edges. The DCO produces output signals with precise duty cycles and minimal distortion because it uses digital control logic rather than analog delay propagation, thereby maintaining frequency multiplication accuracy while eliminating duty cycle errors.
Solution Approach 2:
The patent incorporates feedback mechanisms through the phase detector that monitor the output signal quality and adjust the DCO control accordingly. This feedback loop ensures that the multiplied frequency signal maintains accurate duty cycles and minimal distortion by continuously correcting any deviations introduced during the frequency multiplication process.
Data Source
AI summary
A delay-locked loop (DLL) circuit is disclosed that can generate an output oscillation signal having a frequency that is an integer multiple of an input oscillation signal. The DLL includes a phase detector, a charge pump, and a voltage-controlled oscillator (VCO). The phase detector generates UP and DN control signals in response to a phase difference between a reference signal and a feedback signal. The charge pump generates a control voltage in response to the UP and DN control signals. The VCO adjusts the frequency of the output oscillation signal in response to the control voltage, generates the reference signal in response to the input oscillation signal, and generates the feedback signal in response to the output oscillation signal.