Feedback Clock Path Layout for Low-Power Duty-Cycle Correction
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Solution Overview
Problem
Conventional clock generator circuits with feedback clock paths face issues of reduced responsiveness and increased power consumption due to the introduction of additional transistor circuitry, which affects clock stability and performance.
Innovation Solution
The introduction of a feedback clock path that removes circuitry from the forward path while providing power savings and duty-cycle correction capabilities, using a lower frequency clock signal for phase detection and duty-cycle correction, thereby reducing the overall gate count and propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a feedback clock path is introduced to provide duty-cycle correction and power savings, then power consumption is reduced and duty-cycle correction is achieved, but propagation delay increases and responsiveness decreases
Solution Approach 1:
The clock generator circuit is divided into separate functional blocks: a forward clock path containing delay elements and a feedback clock path containing the phase detector and duty-cycle correction circuitry. This segmentation allows the feedback path to be optimized for power efficiency while the forward path maintains speed, resolving the contradiction between power consumption and responsiveness.
Solution Approach 2:
A feedback clock path acts as an intermediary mechanism that carries phase detection and duty-cycle correction functions separate from the main forward clock path. This intermediary structure enables power savings through selective activation while minimizing impact on the critical forward path speed, addressing both power consumption and responsiveness requirements.
2Adaptability or versatility
If additional transistor circuitry is added for duty-cycle correction and phase detection, then duty-cycle correction capability is improved, but device complexity increases
Solution Approach 1:
The duty-cycle correction circuitry and phase detector are extracted from the forward clock path and placed in a separate feedback clock path. This extraction adds the necessary adaptability for duty-cycle correction while organizing the complexity into a dedicated feedback module, making the overall system more manageable and maintainable.
Solution Approach 2:
The feedback clock path serves multiple functions simultaneously: phase detection, duty-cycle correction, and power management. By consolidating these functions in a single feedback module rather than distributing them throughout the forward path, the patent achieves versatility while controlling overall device complexity through functional integration.
Data Source
AI summary
Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by an adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.