Poly-Phase Sequence Generator Circuit Without Buffer Overhead
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Solution Overview
Problem
Generating poly-phase sequences for synchronization in radio communications systems is costly and inflexible due to the need for extensive buffers and complex hardware.
Innovation Solution
An electronic circuit arrangement using a minimal set of components including adders, multipliers, registers, counters, and a trigonometry device generates poly-phase sequences efficiently, reducing manufacturing costs and enabling fast processing speeds while allowing for flexibility through time displacement and arbitrary counter usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If poly-phase sequences are generated using conventional methods with buffers, then sequence generation is possible, but manufacturing costs increase and flexibility is limited
Solution Approach 1:
The patent implements dynamic configurability through control registers that allow runtime modification of sequence parameters (root index, sequence length, time displacement). This enables the same hardware to generate different poly-phase sequences adaptively without requiring physical reconfiguration or extensive buffering, resolving the contradiction between low manufacturing cost and high flexibility.
Solution Approach 2:
The invention creates a universal sequence generator that can produce multiple types of poly-phase sequences (Zadoff-Chu, CASPER, etc.) using a single integrated circuit with configurable parameters. This multi-functional approach eliminates the need for separate buffers for different sequences, achieving both cost reduction and enhanced adaptability.
2Productivity
If poly-phase sequences are generated using conventional methods, then sequences can be produced, but processing speed decreases due to complex operations
Solution Approach 1:
The patent extracts and eliminates the computationally expensive squaring operation from the sequence generation process by using an alternative mathematical formulation. This removal of complex operations directly increases processing speed while reducing computational complexity, resolving the contradiction between productivity and device complexity.
Solution Approach 2:
The invention replaces complex, time-consuming computational operations with simpler, faster arithmetic operations (multiplication and addition). This substitution of computationally expensive operations with cheaper, faster alternatives increases processing speed without requiring more complex hardware.
3Ease of manufacture
If a minimal circuit design is used, then manufacturing costs decrease, but the ability to generate different sequences may be limited
Solution Approach 1:
The patent achieves high flexibility with minimal hardware by enabling dynamic parameter changes through control registers. Users can modify sequence parameters (root index, length, time displacement) at runtime, allowing a simple circuit to generate diverse poly-phase sequences adaptively, resolving the contradiction between low manufacturing cost and high adaptability.
Data Source
AI summary
The electronic circuit arrangement is used for generating poly-phase sequences as synchronization sequences and/or reference sequences in radio communications systems. It comprises a first adder, a first multiplier, a first register, a second register, a first counter and a trigonometry device. The first adder adds a value (km) formed from the value (k) of the counter to the value (B) of the first register. The first multiplier multiplies the value (A) of the second register by a value (y) formed from the value (B) of the first register and the value (k) of the counter. The trigonometry device forms the real part and the imaginary part of the present value of the poly-phase sequence (ak) from a value formed at least from the output value (wk) of the first multiplier.