Delay-Based Frequency Divider for Odd Integer Clock Division
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Solution Overview
Problem
Conventional frequency synthesizers are limited by frequency dividers that can only achieve even division factors, restricting flexibility and leading to power and area penalties when attempting to double counting frequency for odd division factors.
Innovation Solution
Incorporating a delay unit into the frequency divider system to modify the clock signal, allowing for odd or any integer division factors without significant power or area penalties, while maintaining a 50% duty cycle and maximum input clock frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a frequency divider by two is used to achieve odd division factors, then flexibility is improved, but power consumption and area increase significantly
Solution Approach 1:
The frequency division function is segmented into two independent parts: a conventional frequency divider by two that provides 50% duty cycle output, and a new delay-based circuit that generates the additional phase shift. This segmentation allows each part to be optimized independently, achieving odd division factors without the power and area penalties of doubling the entire counter frequency.
Solution Approach 2:
A delay element is introduced as an intermediary between the frequency divider by two and the final output. This delay element generates a delayed version of the 50% duty cycle signal, and by combining the original and delayed signals through XOR logic, the system achieves odd division factors while maintaining low power consumption and small area footprint.
2Adaptability or versatility
If counting frequency is doubled to achieve odd division factors, then adaptability is improved, but device complexity increases
Solution Approach 1:
The frequency divider by two serves multiple functions: it provides the base frequency division, generates a 50% duty cycle output signal, and creates a signal that can be delayed and combined to achieve odd division factors. This multi-functionality eliminates the need for separate circuits for even and odd division, reducing overall device complexity.
Solution Approach 2:
The system changes the phase parameter of the clock signal through the delay element, rather than changing the frequency parameter. By adjusting the delay amount, the system can achieve different odd division factors without increasing counter width or complexity, maintaining simple circuit design.
3Stability of the object's composition
If a conventional frequency divider by two is used, then duty cycle is maintained at 50%, but division factor is limited to even factors only
Solution Approach 1:
The delay element operates periodically, delaying the 50% duty cycle signal by half the period of the desired odd division frequency. By periodically combining the original and delayed signals, the system generates odd division factors while maintaining the stable 50% duty cycle characteristic of the original frequency divider by two.
Data Source
AI summary
At least one example embodiment provides for a frequency divider system including a delay unit configured to receive a first input clock signal having a first input clock frequency and a requirement and output a modified clock signal, and a frequency divider configured to receive the modified clock signal and output an output clock signal having an output clock frequency. The output clock frequency is an odd or even integer division of the first input clock frequency based on the requirement such as an input control word.