Phase Detection Circuit Switching Clock Comparison Modes Under Noise
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Solution Overview
Problem
Conventional synchronization circuits, such as phase locked loops (PLL) and delayed locked loops (DLL), face operation errors due to noise components like jitter in reference and comparison target signals, leading to unstable phase detection.
Innovation Solution
A phase detection circuit that generates a phase detection signal by comparing a divided clock signal during a control signal's deactivation period and the first and second clock signals during its activation period, using a multiplexing section to select between the divided and undivided clock signals, and a detection section to compare these signals, ensuring stable operation despite noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase detection circuit compares reference clock signal and feedback clock signal continuously, then phase detection function is maintained, but noise components cause operation errors and instability
Solution Approach 1:
The phase detection circuit operates periodically by enabling phase detection only during specific time periods when the control signal is active. The circuit alternates between phase detection periods and non-detection periods, which reduces the impact of continuous noise while maintaining necessary phase detection functionality for synchronization circuit operation.
Solution Approach 2:
The circuit enables phase detection in advance during initialization or setup phases when the control signal is active, establishing proper synchronization before normal operation begins. This preliminary phase detection ensures the circuit is properly configured before encountering potential noise issues during steady-state operation.
2Object-affected harmful factors
If phase detection is performed during activation period only, then noise impact is reduced, but phase detection coverage is limited
Solution Approach 1:
The phase detection circuit dynamically adjusts its operation based on the control signal state. During activation periods, the circuit performs phase detection with full functionality. During deactivation periods, the circuit modifies its operation to reduce noise impact while maintaining essential detection capabilities, allowing adaptive response to operational conditions.
Data Source
AI summary
A phase detection circuit is configured to generate a phase detection signal by comparing a divided clock signal obtained by dividing a first clock signal to a second clock signal during a deactivation period of a control signal, and generate the phase detection signal by comparing the first and second clock signals during an activation period of the control signal.