Timing Recovery Loop Acceleration for Faster Phase and Frequency Tracking

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Solution Overview

Problem

Timing recovery circuits in high-speed serializers/deserializers face latency issues due to processing delays in loop filtering, which reduce loop bandwidth and jitter tolerance, making them less power-efficient and cost-effective.

Innovation Solution

Incorporating phase and frequency tracking accelerators into the timing recovery circuit to compute phase and frequency variations during the delay period of the loop filter, either in direct-form or using pre-computed look-up tables, to eliminate processing delays and enhance loop bandwidth and jitter tolerance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If additional delay stages are inserted into critical paths to ease timing closure, then setup and hold time requirements are met, but loop latency increases and processing speed decreases

Engineering Contradiction:
Improvetiming closureVSAvoidloop latency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent pre-computes phase and frequency variations during the delay period using accelerators that operate in parallel with the loop filter. By performing the tracking computation beforehand and storing results in buffers, the system eliminates the need for additional delay stages while meeting timing requirements.

Inventive Principle:
Principle #10Preliminary action

2Speed

If high-speed cells are used instead of low-speed cells, then setup and hold time requirements are met, but power consumption increases

Engineering Contradiction:
Improvecell operating speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent divides the timing recovery function into two independent segments: the loop filter that maintains original speed characteristics, and the phase/frequency tracking accelerators that operate in parallel. This segmentation allows low-speed cells to be used in the main path while power consumption remains controlled.

Inventive Principle:
Principle #1Segmentation

3Reliability

If loop bandwidth is increased to improve jitter tolerance, then tracking performance improves, but loop latency increases and stability decreases

Engineering Contradiction:
Improvejitter toleranceVSAvoidloop stability
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent introduces phase and frequency tracking accelerators as intermediary components that compute tracking variations during the loop filter delay period. These accelerators act as mediators that provide advance compensation for phase and frequency changes, allowing the loop to respond faster without increasing overall latency or compromising stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Productivity

If processing delay of loop filtering is reduced to accelerate phase tracking, then loop bandwidth increases, but timing closure becomes more difficult

Engineering Contradiction:
Improvephase tracking speedVSAvoidtiming closure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent creates a parallel copy of the tracking function through accelerators that compute phase and frequency variations independently during the delay period. This copying approach allows the main loop filter to maintain its original processing delay while the accelerators provide accelerated tracking information, avoiding timing closure issues.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8670512B1Acceleration of phase and frequency tracking for low-latency timing recovery
Publication Date: 2014.03.11 MICROSEMI SOLUTIONS US INC
  • US8670512B1 patent drawing
  • US8670512B1 patent drawing
  • US8670512B1 patent drawing

AI summary

Circuit and methods accelerate jitter tracking and reduce or eliminate the processing delay of loop filtering in timing recovery. A timing recovery circuit incorporates a phase tracking accelerator and a frequency tracking accelerator to compute the phase and frequency variation of incoming signal during the delay period of a loop filter. In one embodiment, phase and frequency tracking accelerators are realized in direct forms. In another embodiment, pre-computed look-up tables are employed in phase and frequency tracking accelerators to ease timing closure and simplify accelerator circuit. The phase tracking accelerator and the frequency tracking accelerator together compensate the estimated phase at the output of a loop filter and eliminate the processing delay of loop filtering. The loop bandwidth and jitter tolerance of timing recovery are increased.