Digital Delay Locked Loop With Segmented Phase Detection
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Solution Overview
Problem
Digital delay locked loops face limitations in reducing the maximum static phase offset due to a large detection window size, which is influenced by process voltage temperature (PVT) variations, leading to inferior jitter performance compared to analog loops.
Innovation Solution
A digital delay locked loop design that generates multiple delay signals with different phases, divides the detection window into finer areas, and uses phase synthesizing and detection parts to generate control codes, allowing for precise phase adjustment and reduced static phase offset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the detection window size is increased to account for PVT variations, then the reliability of locking the reference signal is improved, but the maximum static phase offset increases
Solution Approach 1:
The detection window is divided into multiple sub-detection windows (first, second, and third sub-detection windows) along the phase axis. Each sub-detection window corresponds to a specific phase range, allowing the system to achieve fine-grained phase detection with smaller effective detection window size in each segment, thereby reducing maximum static phase offset while maintaining overall locking reliability through comprehensive coverage.
2Measurement precision
If the detection window size is decreased to reduce static phase offset, then the measurement precision is improved, but the reliability of locking under PVT variations deteriorates
Solution Approach 1:
The system dynamically adjusts the detection strategy by implementing multiple detection windows that can adapt to different phase conditions. The phase detection part selectively uses appropriate sub-detection windows based on the current phase relationship between reference and feedback signals, enabling the system to maintain high precision while accommodating PVT variations through dynamic detection window selection rather than relying on a single large static window.
3Measurement precision
If multiple delay signals with different phases are generated, then the phase detection precision is improved, but the device complexity increases
Solution Approach 1:
The delay locked loop is segmented into distinct functional modules: delay signal generation part, phase synthesizing part, and phase detection part. Each module handles specific tasks, and the phase synthesizing part generates multiple delay signals with different phases by combining outputs from fine delay lines. This modular segmentation manages complexity by organizing the signal generation process into manageable, independent sections rather than a monolithic complex structure.
Data Source
AI summary
A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal.