PLL VCO Calibration for Fast TDD Mode Switching

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Solution Overview

Problem

Cellular phones face challenges in calibrating voltage controlled oscillators (VCOs) within phase locked loops (PLLs) when transitioning between transmit and receive modes of operation, as existing communication standards often do not provide sufficient time for full calibration, leading to misalignment with the appropriate receive frequency.

Innovation Solution

Implementing three calibration types: full calibration, fine calibration, and offset calibration, where the controller module adjusts the VCO to quickly lock onto the reference signal within the time constraints specified by various communication standards, using a combination of scaled-down versions of full calibration and pre-determined offsets to compensate for mode transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If full calibration is performed during mode transitions, then frequency alignment accuracy is improved, but calibration time exceeds the time window provided by communication standards

Engineering Contradiction:
Improvefrequency alignment accuracyVSAvoidcalibration time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The calibration process is segmented into three distinct types: full calibration (performed during initial channel engagement), fine calibration (performed when sufficient time is available), and offset calibration (performed when time is limited). This segmentation allows the system to select the appropriate calibration depth based on available time, resolving the contradiction between achieving full frequency alignment accuracy and completing calibration within the time window provided by communication standards.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of always performing complete full calibration during mode transitions, the system applies partial calibration actions (fine calibration or offset calibration) that provide sufficient frequency alignment for the specific transition scenario. This partial action approach achieves adequate frequency alignment accuracy without exceeding the time constraints imposed by communication standards.

Inventive Principle:
Principle #16Partial or excessive action

2Productivity

If VCO calibration is performed quickly during mode transitions, then time constraints are satisfied, but frequency alignment accuracy deteriorates

Engineering Contradiction:
Improvecalibration speedVSAvoidfrequency alignment accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The calibration approach is made dynamic by automatically selecting between fine calibration and offset calibration based on the available time window during mode transitions. When sufficient time is available, fine calibration provides higher frequency alignment accuracy; when time is constrained, offset calibration provides faster calibration with adequate accuracy. This dynamic selection resolves the contradiction between calibration speed and frequency alignment accuracy.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the calibration parameter (depth of calibration) based on the time available. By adjusting the calibration parameter from full (initial calibration) to fine (partial recalibration) to offset (minimal adjustment), the system optimizes the balance between calibration speed and frequency alignment accuracy for different operational scenarios.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8611842B2Apparatus and method for fast phase locked loop (PLL) settling for cellular time-division duplex (TDD) communications systems
Publication Date: 2013.12.17 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8611842B2 patent drawing
  • US8611842B2 patent drawing
  • US8611842B2 patent drawing

AI summary

A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation.