Current-Mirror Level Shifter for Compact Low-Power Voltage Translation
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Solution Overview
Problem
Conventional level shifters require larger layout areas and higher power consumption due to the limited current driving ability of p-channel transistors and the need for customized circuit designs for different voltage ranges, making them inefficient and inflexible for various applications.
Innovation Solution
A level shifter design utilizing current mirrors to control the conduction of transistors, allowing for reduced layout area and adaptable circuit design across different applications by using current driving instead of voltage driving, with transistors matched to provide specific currents for efficient signal range expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the transistor TP1 increases its current conduction to pull the voltage of node n1 up against the turned-on transistor TN1, then the voltage level can be shifted properly, but the layout area of the transistors increases due to the larger aspect ratio required
Solution Approach 1:
The patent changes the control parameter from voltage-driven to current-driven operation. By controlling the gate voltage of TP1 through a current mirror circuit that references TN1's current, the system achieves better current matching without requiring TP1 to have a larger aspect ratio. This parameter transformation resolves the contradiction by enabling adequate current driving ability with smaller transistor dimensions.
2Power
If the transistor TP1 conducts more current to compete against transistor TN1 during signal transition, then the voltage level shifting is achieved, but the short current increases causing higher power consumption
Solution Approach 1:
The patent implements a feedback mechanism where the gate voltage of TP1 is controlled by a current mirror that continuously monitors and replicates the current through TN1. This feedback ensures that TP1 only conducts the necessary current to match TN1's conduction, preventing excessive current flow and reducing short current losses during transitions, thereby lowering power consumption while maintaining level shifting capability.
3Reliability
If the level shifter is designed with voltage driving for specific voltage ranges, then the circuit operates correctly for that application, but the design cannot be adapted to different voltage ranges requiring re-design
Solution Approach 1:
The patent creates a universal level shifter design that can operate across different voltage ranges by using current-driven operation with current mirror circuits. The same basic circuit topology can be applied to various applications (e.g., 0-3V to -3-3V, or 0-3V to -20-3V) by simply adjusting current parameters rather than redesigning the entire circuit, thus achieving both reliability and adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the layout area and power consumption while enabling a single circuit design to handle various voltage level shifting applications, improving efficiency and flexibility.
Implementation Method 1
A level shifter design utilizing current mirrors to control the conduction of transistors, allowing for reduced layout area and adaptable circuit design across different applications by using current driving instead of voltage driving
Data Source
AI summary
The present invention provides a level shifter. In an embodiment, the level shifter includes first to sixth transistors. The first and second transistors have common control nodes coupled to a first bias voltage, receive a pair of input signals and respectively provide a first output node and a second output node. The fifth and sixth transistors have common control nodes coupled to a second bias voltage to form a current mirror. The third transistor is coupled between the first and the fifth transistors and has a control node coupled to the second output node. The fourth transistor is couple between the second and the sixth transistors and has a control node coupled to the first output node.