Fractional-N PLL Phase Offset Correction After Loss of Lock
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Solution Overview
Problem
PLL synthesizers with fractional-N frequency dividers face challenges in maintaining phase coherence across state-of-lock intervals separated by loss-of-lock intervals, leading to phase shifts in the synthesizer signal, which complicates signal processing and data extraction, especially in applications like GNSS receivers.
Innovation Solution
A method to determine and compensate for phase offsets caused by sudden loss of lock, allowing for phase-coherent signal correction across transitory loss periods, independent of implementation details and without temporal restrictions on switching between divide ratios, using a cycle count signal to derive an offset term and adjust the numerically controlled oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fractional-N frequency divider is used to achieve fine frequency resolution, then the frequency spacing can be narrowed, but phase coherence is lost during loss-of-lock intervals
Solution Approach 1:
A cycle counter is introduced as an intermediary component that counts the number of cycles of the synthesizer signal and reference signal during loss-of-lock intervals. This cycle count serves as a mediator to calculate the phase offset, enabling phase coherence to be restored without compromising the fine frequency resolution provided by the fractional-N frequency divider.
Solution Approach 2:
The cycle counter continuously counts cycles during loss-of-lock intervals before the PLL relocks. This preliminary counting action allows the phase offset to be calculated and compensated in advance, ensuring phase coherence is maintained when the PLL transitions back to the locked state, without affecting the frequency resolution capability.
2Use of energy by moving object
If the PLL is allowed to experience loss-of-lock intervals for power saving or reconfiguration, then energy consumption or adaptability is improved, but phase coherence between intervals is degraded
Solution Approach 1:
The cycle counter acts as an intermediary that continues to track cycle differences during loss-of-lock intervals when the PLL is suspended for power saving. This allows the phase offset to be accurately measured even when the PLL is not actively maintaining lock, enabling phase coherence to be restored upon relocking without continuous power consumption during the loss-of-lock period.
3Adaptability or versatility
If switching between different divide ratios is enabled dynamically, then frequency adaptability is improved, but phase coherence is compromised due to unforeseen loss of lock
Solution Approach 1:
The system uses feedback from the cycle counter to continuously monitor and detect loss-of-lock events that occur during dynamic frequency switching. The calculated phase offset from the cycle count is fed back to correct the synthesizer signal, ensuring that phase coherence is maintained even when unforeseen loss of lock occurs during adaptive frequency changes.
Data Source
AI summary
A fractional-N PLL synthesizer has an up-down counter counting up for positive edges of a frequency-divided signal produced by a frequency divider with a fractional divide ratio in a feedback path of the synthesizer and down for positive edges of a reference signal. A phase offset between portions of the synthesizer signal before and after a loss-of-lock interval is then assessed as a numerical value proportional to the product of the divide ratio and the cycle difference registered by the up-down counter (36) after the loss-of-lock interval. A correction term derived from the phase offset can be used in a signal processing device as employed, e.g., in a GNSS receiver, for producing, from an analog input signal, a phase-corrected baseband signal where portions of the signal before and after loss of lock are phase coherent.