Analog Phase Interpolator Bias Steering for Low-Voltage CDR
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Solution Overview
Problem
Conventional clock data recovery circuits face challenges in implementing a low supply voltage analog phase interpolator, which is essential for efficient data alignment and synchronization.
Innovation Solution
The proposed solution involves a circuit comprising a first and second phase circuit, along with a current steering circuit that generates bias signals to produce a phase interpolated clock signal, allowing the analog phase interpolator to operate at low voltage supplies and respond to digital control signals within a clock data recovery circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional phase interpolator circuits are used, then the circuit can generate phase interpolated clock signals, but the supply voltage requirement is high and headroom is insufficient
Solution Approach 1:
The phase interpolator is divided into multiple independent phase circuits (first phase circuit, second phase circuit, etc.), each generating a portion of the phase interpolated clock signal. This segmentation allows each circuit to operate with lower voltage requirements while maintaining overall system performance through parallel operation and feedback control.
2Measurement precision
If the number of phase circuits is increased to improve phase resolution, then phase interpolation precision is improved, but circuit complexity and power consumption increase
Solution Approach 1:
Multiple phase circuits are merged into a unified phase interpolator system with a shared feedback mechanism and common output stage. The phase detector output feeds back to control all phase circuits simultaneously, allowing them to work cooperatively to achieve high precision phase interpolation without proportionally increasing overall circuit complexity.
3Use of energy by moving object
If conventional biasing schemes are used, then the phase interpolator can operate, but it requires high supply voltage and cannot meet low headroom specifications
Solution Approach 1:
The biasing parameters of the phase circuits are optimized to enable operation at low supply voltages. By adjusting the bias current and voltage parameters, the circuits achieve proper operating points with reduced voltage headroom requirements, allowing the phase interpolator to function correctly at lower supply voltages than conventional designs.
Data Source
AI summary
An apparatus comprising a first phase circuit, a second phase circuit, and a current steering circuit. The first phase circuit may be configured to generate a first portion of a phase interpolated clock signal in response to (i) a control signal, (ii) a first bias signal, and (iii) a feedback of said phase interpolated clock signal. The second phase circuit may be configured to generate a second portion of the phase interpolated clock signal in response to (i) the control signal, (ii) a second bias signal, and (iii) the feedback of the phase interpolated clock signal. The current steering circuit may be configured to generate the first bias signal and the second bias signal in response to a reference bias signal.