Clock Supply Locking Control for Low-Power Semiconductor Memory
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Solution Overview
Problem
Semiconductor devices face limitations in entering power-down mode due to the need for clock supply circuit locking, leading to increased current consumption as internal circuits cannot enter power-down during locking periods.
Innovation Solution
A semiconductor device with a controller that allows internal circuits to enter power-down mode independently of the clock supply circuit, which only enters power-down mode after the clock supply circuit has completed locking, using a power-down signal and locking signal to control this process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the semiconductor device enters power-down mode during clock supply circuit locking period, then current consumption is reduced, but the clock supply circuit cannot generate stable internal clock
Solution Approach 1:
The device is divided into two independent power control groups: the clock supply circuit (DLL/PLL) and the internal circuits (memory blocks, I/O blocks). Each group can enter power-down mode independently based on its own requirements, allowing the internal circuits to save power during locking periods while the clock circuit remains active to maintain clock stability
Solution Approach 2:
The power-down control mechanism is made dynamic and selective rather than uniform. The control circuit receives the power-down signal and generates separate control signals: one for the clock supply circuit that prevents power-down during locking, and another for internal circuits that allows power-down during locking periods. This dynamic control resolves the contradiction by adapting power management to the specific operational state of each circuit component
2Reliability
If the internal circuits operate during clock supply circuit locking period, then clock stability is maintained, but current consumption increases
Solution Approach 1:
The device is divided into two independent power control groups: the clock supply circuit (DLL/PLL) and the internal circuits (memory blocks, I/O blocks). Each group can enter power-down mode independently based on its own requirements, allowing the internal circuits to save power during locking periods while the clock circuit remains active to maintain clock stability
Solution Approach 2:
The power-down control mechanism is made dynamic and selective rather than uniform. The control circuit receives the power-down signal and generates separate control signals: one for the clock supply circuit that prevents power-down during locking, and another for internal circuits that allows power-down during locking periods. This dynamic control resolves the contradiction by adapting power management to the specific operational state of each circuit component
3Loss of energy
If the semiconductor device enters power-down mode during self-refresh mode transition, then power management is improved, but the delay locked loop cannot complete re-locking
Solution Approach 1:
The device is divided into two independent power control groups: the clock supply circuit (DLL/PLL) and the internal circuits (memory blocks, I/O blocks). Each group can enter power-down mode independently based on its own requirements, allowing the internal circuits to save power during locking periods while the clock circuit remains active to maintain clock stability
Solution Approach 2:
The power-down control mechanism is made dynamic and selective rather than uniform. The control circuit receives the power-down signal and generates separate control signals: one for the clock supply circuit that prevents power-down during locking, and another for internal circuits that allows power-down during locking periods. This dynamic control resolves the contradiction by adapting power management to the specific operational state of each circuit component
Data Source
AI summary
A semiconductor device includes a clock supply circuit configured to generate an internal clock by using an external clock, an internal circuit configured to operate in synchronization with the internal clock and enter a power-down mode in response to a power-down signal, and a controller configured to control an entry of the clock supply circuit into the power-down mode in response to a locking signal, which represents that the clock supply circuit has been locked, and the power-down signal.