Master-Slave Digital DLL for Duty-Cycle and Jitter Tolerance
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Solution Overview
Problem
Conventional delay-locked loops (DLLs) in DDR memory interfaces are sensitive to reference clock duty cycle and jitter, leading to area inefficiency and power consumption issues, as well as requiring complex control logic and additional components for phase detection and alignment.
Innovation Solution
The proposed DLL design uses a master-slave configuration with binary weighted differential-delay cells and an averaging circuit to align the DLL tap with the falling edge of the reference clock, reducing area consumption and making the DLL insensitive to duty cycle variations, while also employing an averaging technique to mitigate jitter-induced delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional DLL design is used with phase detector and alignment logic, then phase detection capability is achieved, but area consumption increases and duty cycle sensitivity worsens
Solution Approach 1:
The patent extracts and eliminates the dedicated phase detector and phase alignment logic from the conventional DLL structure. Instead of using separate components for phase detection, the invention uses the existing delay-locked loop control mechanism to achieve phase alignment, thereby removing unnecessary components and reducing core area while maintaining phase detection capability
Solution Approach 2:
The control logic in the proposed DLL serves multiple functions: it controls the delay line, performs phase detection implicitly, and achieves phase alignment all through a single control mechanism. This multi-functionality eliminates the need for separate phase detector and alignment components, reducing area consumption
2Manufacturing precision
If conventional DLL with complex control logic is used, then phase alignment is achieved, but device complexity increases
Solution Approach 1:
The patent removes complex phase alignment logic and dedicated control circuits from the conventional DLL design. The simplified control mechanism directly adjusts the delay line without requiring separate alignment stages, thereby reducing device complexity while maintaining alignment precision
Solution Approach 2:
Instead of using complex forward control logic to achieve phase alignment, the invention inverts the approach by using the feedback from the delay line output directly to control the delay elements. This inverted control mechanism simplifies the logic while achieving the same alignment precision
3Measurement precision
If DLL is sensitive to reference clock duty cycle, then phase detection accuracy may improve, but reliability under varying conditions worsens
Solution Approach 1:
The patent implements a dynamic control mechanism that continuously adjusts the delay line based on the actual clock edges detected, rather than relying on fixed duty cycle assumptions. This dynamic adaptation allows the DLL to maintain accurate phase detection and alignment regardless of duty cycle variations, improving reliability under varying conditions
Solution Approach 2:
The invention changes the operating parameter from fixed duty cycle dependency to variable edge detection. By detecting actual rising and falling edges and adjusting delay accordingly, the system becomes insensitive to duty cycle parameter variations while maintaining detection accuracy
4Measurement precision
If additional components for phase detection are added, then phase detection capability improves, but power consumption increases
Solution Approach 1:
The control logic serves multiple functions including delay control, phase detection, and alignment, eliminating the need for separate power-consuming phase detector components. This multi-functional approach maintains detection capability while reducing overall power consumption
Solution Approach 2:
The patent extracts and removes dedicated phase detector components from the design, using the existing control logic to perform phase detection functions instead. This elimination of redundant components directly reduces power consumption while preserving detection capability
Data Source
AI summary
A circuit comprising 1) a master delay-locked loop comprising a phase detector for receiving a reference clock and generating an output, control logic for receiving the output from the phase detector and a delta delay input and generating a control output, a clock splitter for receiving the reference clock and generating differential clock output, a delay line for receiving the differential reference clock from the clock splitter and generating n phases of differential reference clock at output, a multiplexer for receiving the output from the delay line and the control logic output and generating a clock output, wherein the phase detector is for receiving the reference clock, and 2) a slave delay-locked loop for receiving the control logic output and a strobe input and generating a delay locked loop output.