Delay Line Feedback Selection for Clock Frequency and Duty Cycle Locking
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Solution Overview
Problem
Conventional delay locked loops cannot adjust the frequency of output clock signals while maintaining a fifty percent duty cycle, leading to increased chip size and potential interference when incorporating a phase locked loop for frequency multiplying functions.
Innovation Solution
A delay line circuit with a feedback selection section and adjustable control voltage, allowing for frequency adjustment of output clock signals by selectively delaying input or feedback clock signals through a series of delay units, and a phase detection mechanism to maintain duty cycle and frequency locking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase locked loop is added to provide frequency multiplying function, then the frequency adjustment capability is improved, but the chip size increases and clock signals may interfere with each other
Solution Approach 1:
The patent combines the frequency multiplying function and duty cycle maintaining function into a single integrated circuit by adding a feedback selection section to the delay locked loop. This merging eliminates the need for a separate phase locked loop, thereby reducing chip size while maintaining both frequency adjustment capability and duty cycle stability.
Solution Approach 2:
The delay locked loop is designed to perform multiple functions simultaneously: duty cycle maintaining, frequency multiplying, and frequency adjustment. By making the circuit universal and capable of handling multiple tasks, the patent avoids the need for additional dedicated circuits, thus preventing chip size increase.
2Adaptability or versatility
If a phase locked loop is added to provide frequency multiplying function, then the frequency adjustment capability is improved, but clock signals between delay locked loop and phase locked loop may interfere with each other
Solution Approach 1:
By merging the frequency multiplying function into the delay locked loop itself rather than using a separate phase locked loop, the patent eliminates the interaction between two separate loops. This integration removes the source of clock signal interference while preserving the frequency multiplying capability.
3Adaptability or versatility
If the delay line circuit uses feedback mechanism, then the frequency adjustment range is improved, but the circuit complexity increases
Solution Approach 1:
The patent introduces a feedback mechanism where the output clock signal is fed back to the delay line section through a feedback selection section. This feedback enables the circuit to adjust its own operating parameters dynamically, expanding the frequency adjustment range. The feedback is implemented in a controlled manner that manages circuit complexity.
Solution Approach 2:
The circuit incorporates dynamic elements including a feedback selection section that can switch between different feedback paths based on operating conditions. This dynamic configuration allows the circuit to adapt its complexity level and feedback path according to the required frequency adjustment range, optimizing performance while managing complexity.
Data Source
AI summary
The invention provides a delay line circuit. The delay line circuit includes a delay line section and a feedback selection section. The delay line section receives an input clock signal and a feedback clock signal and delays one of the input clock signal and the feedback clock signal to generate an output clock signal, wherein the delay line section includes a plurality of delay units coupled in series. The feedback selection section is coupled to the delay line section and feedbacks the output clock signal to one of the delay units to serve as the feedback clock signal based on a selection signal. Wherein, one of the input clock signal and the feedback clock signal is delayed by a specific number of the delay units based on the selection signal to changes the frequency of the output clock signal.