Mux/Demux Clock Divider Reset for Deterministic Bit Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multiplexor/demultiplexor circuits face challenges in maintaining bit alignment due to random states of internal clock dividers, leading to increased power consumption and difficulty in scaling, as well as complexities in designing and testing clocking circuits.
Innovation Solution
A circuit and method utilizing an asynchronous reset signal to set clock dividers to a known state, employing a chain of cascading units and clock gating circuits to generate and manage clock signals, ensuring bit alignment across multiple multiplexor/demultiplexor blocks in parallel configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a common clock divider circuit is implemented to generate all required clocks, then bit alignment is achieved, but power consumption increases and routing complexity increases
Solution Approach 1:
The patent divides the clock generation function into separate divider circuits within each multiplexor/demultiplexor block, with each block independently generating its own clocks. This segmentation eliminates the need for a single common clock divider, reducing power consumption and routing complexity while maintaining bit alignment through synchronized reset of all divider circuits.
2Stability of the object's composition
If a common clock divider circuit is implemented to generate all required clocks, then bit alignment is achieved, but device complexity increases
Solution Approach 1:
The patent segments the clock generation function across multiple independent divider circuits, one in each multiplexor/demultiplexor block. This eliminates the complex routing required for a single common clock divider to reach all blocks, as each block locally generates its clocks. Bit alignment is maintained through synchronized reset of all dividers.
3Stability of the object's composition
If local clock generation is implemented in each macro, then bit alignment can be achieved, but power consumption increases due to multiple long clock networks
Solution Approach 1:
The patent implements local clock generation by placing a divider circuit within each multiplexor/demultiplexor block, segmenting the clock generation function. This eliminates the need for multiple long distributed clock networks, reducing power consumption while maintaining bit alignment through synchronized reset of all local dividers.
4Ease of operation
If traditional clocking circuits are used that start up in random state, then circuit operation is simple, but automated testing becomes difficult
Solution Approach 1:
The patent applies a synchronized reset signal to all divider circuits before normal operation begins. This preliminary action sets all dividers to a known initial state, ensuring predictable circuit behavior at startup. This enables automated testing by providing a deterministic starting condition against which circuit outputs can be compared, while requiring minimal changes to the operational circuit design.
Data Source
AI summary
Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.