Clock Trimming Switch Array for Low-Leakage Frequency Control
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Solution Overview
Problem
Semiconductor switches used in trimming circuits for internal clock sources, such as relaxation oscillators, face significant current leakage due to sub-threshold conduction in sub-micron devices, which affects the accuracy of the clock signal, especially in low voltage threshold (LVT) devices.
Innovation Solution
A semiconductor switch array comprising PMOS and NMOS devices, where PMOS devices are binary-weighted and NMOS devices are not, with dummy NMOS devices connected to reduce parasitic capacitance, and high voltage threshold NMOS devices are used to minimize current leakage, while maintaining linear trimming capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sub-micron devices with smaller transistor channel lengths are used to reduce device area and increase switching speed, then integration density and switching performance are improved, but current leakage increases due to sub-threshold conduction
Solution Approach 1:
The patent combines PMOS and NMOS devices in parallel within the same switch block to form a composite switching structure. This merging allows the circuit to leverage the fast switching characteristics of sub-micron devices while the complementary device structure helps mitigate sub-threshold conduction effects, reducing overall current leakage compared to using single-device-type switches.
Solution Approach 2:
The patent employs composite device structures by pairing PMOS and NMOS transistors together in the switching array. This composite approach creates a hybrid switching mechanism that combines the advantages of both device types, achieving faster switching times while the opposing carrier types help balance and reduce the net sub-threshold leakage current.
2Use of energy by moving object
If low voltage threshold (LVT) devices are used to reduce voltage requirements, then power consumption is reduced, but current leakage increases significantly
Solution Approach 1:
The patent merges LVT PMOS and NMOS devices in parallel configurations. While LVT devices enable lower operating voltages and reduced dynamic power consumption, the parallel combination with complementary devices helps offset the increased sub-threshold leakage that would occur with LVT devices alone, achieving a balance between power efficiency and leakage control.
3Measurement precision
If trimming switches are used to compensate for capacitor process variation, then oscillator frequency accuracy is improved, but current leakage from the switches affects clock accuracy
Solution Approach 1:
The patent implements trimming switches using parallel PMOS-NMOS pairs instead of single-device switches. This merged structure provides the necessary switching function for frequency trimming while reducing the net current leakage compared to conventional single-type switches, thereby improving clock accuracy by minimizing leakage-induced frequency shifts.
Solution Approach 2:
The patent changes the electrical parameters of the switching devices by using complementary PMOS and NMOS devices with different threshold voltage characteristics and conduction behaviors. This parameter diversification allows the trimming circuit to achieve accurate frequency control while the opposing characteristics of the two device types help cancel out some of the leakage effects.
Data Source
AI summary
A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.