Analog DFT Architecture Using Functional Pins for Shared Test Access
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Solution Overview
Problem
The increasing complexity of integrated circuits, particularly automotive ICs, necessitates a reduction in the number of testability resources and test time while ensuring high-quality testing of analog circuits such as DACs, ADCs, and comparators, which is challenging due to the need for dedicated test pins and equipment.
Innovation Solution
A DFT architecture that reuses functional analog pins for testing by connecting them to an analog test bus, allowing parallel testing of multiple circuits without dedicated test pins, and utilizing built-in self-test solutions to reduce overhead and test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated test pins and equipment are used for testing analog circuits, then testing quality and reliability are improved, but device complexity and test time increase
Solution Approach 1:
The patent makes functional analog pins serve dual purposes: they operate as normal functional pins during functional modes and as test access points during test modes. The test controller dynamically reconfigures the analog test bus to connect to different analog circuits under test, allowing the same physical pin to provide both functional operation and test capability without requiring separate dedicated test pins for each analog circuit.
2Adaptability or versatility
If dedicated test pins are provided for each analog circuit, then testing capability is improved, but the number of pins and test time increase
Solution Approach 1:
The patent implements dynamic reconfiguration of the analog test bus through a test controller that can switch connections in real-time. During test mode, the test controller selectively connects the analog test bus to different analog circuits under test, enabling multiple circuits to be tested sequentially through a single shared test pin. This dynamic switching capability allows versatile testing of multiple circuits without requiring proportional increases in the number of physical test pins.
3Device complexity
If functional analog pins are reused for testing, then device complexity is reduced, but testing capability may be limited
Solution Approach 1:
The patent introduces an analog test bus as an intermediary component that bridges the functional analog pins and the analog circuits under test. This test bus acts as a mediator that can be dynamically connected to different circuits through controlled switches or multiplexers, enabling a single functional pin to access multiple circuits without direct dedicated connections. The intermediary test bus preserves the simplicity of reusing functional pins while maintaining the versatility to test multiple different analog circuits.
Data Source
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AI summary
An integrated circuit, IC, (100) includes: a first functional analog pin or pad (152); a first analog test bus (162) coupled to the first functional analog pin or pad; first and second analog circuits (124, 134, 144) coupled to the first analog test bus (162); and a test controller (110) configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus (162) so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad (152), and keep disconnected an input or output of the second analog circuit from the first analog test bus (162), and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits (124, 134, 144) to the first analog test bus (162) to test the first and second analog circuits using the first analog test bus (162).