Analog-Digital Neural Array Using In-Memory Synaptic Weights
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Solution Overview
Problem
The development of high-performance artificial neural networks is hindered by a lack of adequate hardware technology, particularly in terms of energy efficiency and scalability, as existing digital supercomputers and CMOS circuits are inefficient and bulky for the high connectivity required by neural networks.
Innovation Solution
The use of non-volatile memory arrays, such as non-volatile memory cells configured to operate as synapses, allows for continuous programming and individual tuning of memory states, enabling precise weight adjustments in neural networks, and eliminates the need for separate multiplication and addition logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but energy efficiency deteriorates and hardware complexity increases
Solution Approach 1:
The patent merges memory and computation functions into a single integrated structure where non-volatile memory cells serve dual purposes: storing synaptic weights and performing analog multiplication operations. This eliminates the need for separate digital processing units, thereby improving energy efficiency while maintaining high computational parallelism through the memory array's inherent parallel architecture.
Solution Approach 2:
The patent replaces digital mechanical/logical computation systems with analog electrical computation based on Ohm's law and Kirchhoff's current law. The memory cells perform analog multiplication and addition operations directly in the analog domain, avoiding the energy-intensive digital-to-analog and analog-to-digital conversion processes required by digital supercomputers.
2Productivity
If digital supercomputers or specialized graphics processing unit clusters are used to achieve high connectivity between neurons, then computational parallelism is improved, but device complexity deteriorates
Solution Approach 1:
The patent combines multiple functional components (synaptic weight storage, multiplication logic, addition logic) into a single non-volatile memory cell structure. Each memory cell inherently performs both storage and computation functions, eliminating the need for separate logic circuits and reducing overall hardware complexity while enabling high computational parallelism across the memory array.
Solution Approach 2:
The non-volatile memory cells are designed to serve multiple functions: storing synaptic weights, performing analog multiplication, and contributing to summation through parallel current addition. This multi-functionality reduces the number of dedicated components needed, thereby simplifying the overall system architecture while maintaining high computational capability.
3Use of energy by moving object
If non-volatile memory arrays are used for analog computation, then energy efficiency is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent implements feedback mechanisms during the programming process where the actual weight values stored in memory cells are read and compared against target values. Iterative adjustment algorithms modify the stored weights based on feedback from previous readings, enabling precise weight tuning despite variations in manufacturing processes and ensuring accurate analog computation.
Solution Approach 2:
The patent utilizes the continuous analog nature of non-volatile memory cell characteristics (such as resistance or conductance) to represent synaptic weights. By programming these physical parameters to specific values through controlled electrical pulses, the system achieves precise weight representation and enables fine-grained adjustment of connection strengths in the neural network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances energy efficiency and reduces hardware complexity by integrating memory cells that perform in-situ computation, facilitating high computational parallelism and precise weight tuning in neural networks.
Implementation Method 1
Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate
Data Source
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AI summary
Numerous examples are described for providing an artificial neural network system comprising an analog array and a digital array. In certain examples, an analog array and a digital array are coupled to shared bit lines. In other examples, an analog array and a digital array are coupled to separate bit lines.