Programmable Analog FIR Filter With Pulse-Width Coefficients
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Solution Overview
Problem
Conventional analog filters require multiple gain stages to achieve high-order filtering, which complicates RF receivers and struggles to meet power consumption and signal-to-noise ratio optimization, especially in IoT applications.
Innovation Solution
A programmable analog FIR filter with a single transconductance stage and multiple integrating capacitors, where digital gate signals control analog switches to transmit current signals proportional to filter coefficients, allowing for efficient filtering and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog filters use multiple gain stages to achieve high-order filtering, then the filtering performance is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent replaces conventional voltage-based gain stages with a current-mode integrating architecture. Instead of using multiple voltage amplification stages, the invention uses current sources that are directly integrated into capacitors, eliminating the need for sequential gain stages while achieving the same high-order filtering effect through the integration process itself.
Solution Approach 2:
The invention changes the fundamental operating parameter from voltage to current. By using current-mode operation with transconductance devices and integrating capacitors, the system achieves high-order filtering without requiring multiple voltage gain stages, thereby reducing complexity while maintaining filtering performance.
2Reliability
If conventional analog filters use multiple gain stages, then high-order filtering is achieved, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry voltage gain stages with energy-efficient current-mode integrating circuits. The current sources charge capacitors directly during integration periods and discharge them during reset periods, eliminating the continuous power consumption associated with multiple voltage amplification stages while maintaining the required filtering performance.
Solution Approach 2:
The invention employs periodic integration and reset cycles. Current sources are activated only during specific time windows to charge integrators, followed by reset phases where capacitors are discharged. This periodic operation significantly reduces average power consumption compared to continuous operation of multiple gain stages, while still achieving the necessary high-order filtering effect.
3Use of energy by stationary object
If a single variable-gain stage is used to reduce complexity, then power consumption is reduced, but the receiver complexity increases
Solution Approach 1:
The patent replaces the proposed single variable-gain stage with a current-mode integrating architecture that uses multiple simple current sources and capacitors. This approach achieves the desired power reduction while avoiding the complexity increase associated with variable-gain control circuitry, as the current sources can be implemented as simple switched current mirrors driven by digital control signals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution simplifies the filter design, reduces power consumption, and improves signal-to-noise ratio by decoupling the output sample rate from the bandwidth, enabling efficient channel selection in RF receivers.
Implementation Method 1
a first transconductance device configured to generate a first current signal proportional to the input signal
Implementation Method 2
a first integrating capacitor
Data Source
AI summary
A FIR filter (15), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commuted in n by a first digital gate signal (ϕ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ1) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.