Transversal Filters TRIZ Cases

A passive filter between FFE taps mimics extra postcursor taps to improve ISI compensation without raising power consumption.

Using impedance-based compute-in-memory equalization before digitization cuts digital multiplier load, power use, and routing congestion in Wireless I/O.

A reversible unbinding and search-in-superposition flow uses one codebook to refine codevector estimates with lower memory use and faster processing.

A clocked integrator and sample-and-hold loop removes low-frequency ripple on chip while preserving DC accuracy and fast startup.

Pulse-width digital gate signals set FIR coefficients in a current-mode analog filter, cutting gain-stage complexity, power use, and RF receiver noise.

Different power terminal areas equalize capacitance to ground in a piezoelectric resonator, keeping oscillation frequency stable when signals reverse.

Configurable delay lines and gain stages let this analog bi-quad IIR filter avoid ADC/DAC latency and noise while preserving wideband RF processing.

Direct analog filtering with switchable delays and gain stages avoids ADC/DAC noise and latency while preserving wideband RF processing.

Analog time-delay circuits and digitally controlled amplifiers enable RF filtering with low noise, low delay, and compensation for gain and delay drift.

Current-domain coefficient multiplication replaces DAC-heavy FIR stages to cut noise and power while extending dynamic range.

Digital closed-loop control tunes analog gain and delay to deliver flexible RF filtering with lower quantization noise and less processing delay.

Using GaN sample-and-hold and multiplier paths, this FIR filter mitigates co-site transmit interference at high RF power without ADC complexity.

Zero-inserted FIR coefficients extend effective filter length for IQ mismatch correction across target and secondary bands with lower complexity and power.

Distributed summation across cascaded FIR blocks raises filter order for channel equalization without the node complexity and bandwidth limits of analog FIR designs.

Polyphase decomposition turns recursive filters into parallel frame processors, boosting throughput, cutting power use, and avoiding dropped samples.

Parallel filter taps with all-pass filtering and adaptive gain avoid cascade bandwidth loss, noise, and distortion in multi-GHz receivers.

An analog FIR filter between the mixer and ADC improves selectivity and signal-to-noise ratio while relaxing ADC resolution and power demands.

Clock-driven charge sharing and antiparallel feedback sharpen discrete-time filter roll-off while reducing power use and mismatch sensitivity.

Multiple weighted signal paths independently tune gain, phase, and delay over broadband to improve TX-RX isolation and signal purity.

Clock-driven charge sharing between sampling and history capacitors enables high-order passive RF filters with sharper roll-off and lower power use.

By shifting coefficients instead of data samples, this FIR correlator cuts switching activity to save about 75% power and 9% area.

Oversampling and noise shaping move RRAM quantization errors out of baseband to improve MAC accuracy and signal-to-noise ratio.

An amplifier-based delay chain forms weighted analog taps to cut ISI and noise at high data rates with lower power and chip area.

A shunt-inductance FIR input converts reactive impedance to real impedance, enabling RF down-conversion with lower noise bandwidth and better linearity.

A CMOS FIR filter tunes passband width to match changing radar pulse widths, reducing noise and improving range accuracy.