Analog In-Memory Channel Equalization for Low-Power Wireless I/O
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Solution Overview
Problem
The size and power consumption of adaptive channel equalizers in digital baseband Wireless I/O designs pose significant computing and energy bottlenecks, with conventional digital solutions requiring extensive resources and leading to routing congestion due to massive parallelism and complex multiplier configurations.
Innovation Solution
Implementing a compute-in-memory (CiM) approach that performs signal equalization in the analog domain before digitization, utilizing a memory structure with resistive or capacitive impedances to perform multiply and accumulate operations, reducing the need for complex digital multipliers and alleviating routing congestion by operating partially or entirely in the analog realm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital channel equalization is implemented with extensive taps and bitwidths, then equalization performance is improved, but area and power consumption increase significantly
Solution Approach 1:
The patent replaces the digital equalization system with an optical equalization system. Instead of using digital multipliers, adders, and memory structures in the digital baseband, the invention uses optical modulators, optical carriers, and photodetectors to perform equalization operations in the optical domain. This substitution fundamentally changes the physical domain of operation from electrical/digital to optical, enabling high-performance equalization with reduced area and power consumption in the digital baseband.
Solution Approach 2:
The patent moves the equalization function from the digital baseband dimension to an optical dimension by introducing optical carriers and optical modulation. The equalization coefficients are modulated onto optical carriers, and the equalization operations are performed through optical mixing and detection processes. This dimensional transition allows the equalization function to be executed outside the conventional digital baseband architecture, reducing its area and power footprint.
2Speed
If digital channel equalization uses pipelined and feed-forward structures, then timing is improved and routing congestion is alleviated, but power and area penalty increases
Solution Approach 1:
The patent replaces the digital pipelined and feed-forward structures with optical processing elements. Instead of digital registers, multiplexers, and combinatorial logic circuits that consume power and occupy area, the invention uses optical modulators, optical carriers, and photodetectors to perform the same timing and routing functions in the optical domain, eliminating the associated power and area penalties.
3Measurement precision
If adaptive channel equalizer size is increased to handle complex wireless channels, then equalization accuracy is improved, but routing congestion and power consumption worsen
Solution Approach 1:
The patent replaces the complex digital equalizer structure with an optical equalization system. The equalization coefficients are modulated onto optical carriers using optical modulators, and the equalization operations are performed through optical mixing and detection. This substitution maintains high equalization accuracy while significantly reducing device complexity and routing congestion in the digital baseband, as the optical domain handles the complex processing requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves higher computational density and better power efficiency, allowing for simplified scaling of parallelism and reduced resource utilization, thereby addressing the bottlenecks and congestion issues in digital baseband designs.
Implementation Method 1
a plurality of impedance devices, each impedance device of the plurality of impedance devices connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein an impedance of each of the plurality of impedance devices represents a filter coefficient
Data Source
AI summary
A radiofrequency frontend device includes a memory array, which includes a plurality of input lines; a plurality of output lines; and a plurality of impedance devices, each impedance device connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein each impedance represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods; and when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages.