Cascaded FIR Filter Architecture for High-Bandwidth Equalization
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Solution Overview
Problem
High-speed communication links face limitations in achievable bitrate due to signal distortion, particularly in analog FIR filter implementations, where increasing filter order leads to node complexity and bandwidth limitations, as well as challenges with delay elements and clock frequency, making it difficult to achieve high-performance equalization.
Innovation Solution
The use of cascaded building blocks with first and second delay elements and scaling devices allows for a higher order transversal filter without increasing node complexity, enabling distributed summation and reducing bandwidth limitations, while allowing for a mixed-mode structure with adjustable delay values and non-linear elements, optimizing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the order of the FIR filter is increased to improve equalization performance, then the filtering capability is improved, but the node complexity increases and bandwidth limitations worsen
Solution Approach 1:
The filter is divided into multiple cascaded stages, where each stage processes a subset of the filter coefficients. This segmentation distributes the computational load across multiple nodes rather than concentrating it at a single summation node, thereby reducing node complexity while maintaining the overall filtering capability for high-order FIR filters
Solution Approach 2:
The patent transforms the traditional single-plane filter structure into a multi-stage cascaded architecture. By adding the dimension of stages (time/sequence dimension), the filter achieves high-order processing capability without increasing the complexity of individual nodes, as each stage operates with reduced complexity and the overall performance emerges from the cascade
2Measurement precision
If the order of the FIR filter is increased to improve equalization performance, then the filtering capability is improved, but the bandwidth limitations worsen
Solution Approach 1:
By segmenting the filter into cascaded stages, each operating at a lower complexity level, the patent avoids creating a single high-complexity bottleneck node that would limit bandwidth. The segmented architecture allows signal processing to proceed through multiple simpler stages, maintaining higher overall bandwidth while achieving high-order filtering performance
3Area of stationary object
If active delay cells are used to reduce circuit area, then the area requirement is reduced, but the achievable speed is limited
Solution Approach 1:
The patent employs clocked active delay cells that operate dynamically at optimized clock frequencies. By carefully designing the clocking scheme and allowing the system to operate at the maximum achievable clock frequency for the given circuit area, the patent achieves high-speed operation while maintaining compact circuit implementation
4Speed
If transmission lines are used to achieve high speed, then the achievable speed is improved, but the circuit area increases significantly
Solution Approach 1:
The patent replaces physical transmission lines (mechanical/electromagnetic field-based delay elements requiring large area) with active delay cells implemented using standard CMOS circuitry. This substitution enables high-speed operation through optimized clocking and circuit design while dramatically reducing the circuit area requirement compared to transmission line implementations
5Measurement precision
If the number of delay elements is increased to achieve higher filter order, then the filtering capability is improved, but the distortion introduced by delay blocks increases
Solution Approach 1:
By segmenting the filter into cascaded stages with fewer delay elements per stage, the patent reduces the cumulative distortion introduced by delay blocks. Each stage introduces minimal distortion, and the cascaded structure maintains signal integrity better than a single high-order stage would, thereby achieving high filtering capability with reduced nonlinear distortion
Data Source
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AI summary
A filter (200) comprising cascaded building blocks (100), for filtering an incoming signal, each building block comprising a first and second delay element (110, 120), a first scaling device (130) between an input node of the first delay element (110) and an output node of the second delay element (120), a second scaling device (140) between an output node of the first delay element (110) and an input node of the second delay element (120). The building block moreover comprises a cross scaling device (150, 160) between the output nodes of the first delay element (110) and of the second delay element (120), and/or between the input nodes of the first delay element (110) and of the second delay element (120). The building block (100) is configured such that, in operation, incoming signals at the input node and output node of the second delay element are summed together.