Switched-Capacitor Filter Network With Negative Feedback Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing discrete time filter networks face limitations in achieving efficient filtering with low power consumption and precise control over filter characteristics, particularly in analog and radio-frequency circuits, where they struggle to provide sharp transitions between passband and roll-off and are sensitive to capacitor mismatches and variations.
Innovation Solution
A discrete time filter network with a capacitor bank and clock-driven switches that implement a predefined number of feedback paths, allowing sequential and antiparallel connections between sampling and history capacitors to provide negative feedback, enabling the realization of low-pass, band-pass, and high-pass filters with enhanced transfer functions and reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional discrete time filter networks are used, then the filter can operate with simple structure, but the transition between passband and roll-off is not sharp and filtering efficiency is limited
Solution Approach 1:
The filter network is segmented into multiple history capacitors (CH0 to CHN) arranged in a cascaded structure, where each capacitor contributes to different stages of the filtering process. This segmentation enables sharper transition characteristics by distributing the filtering function across multiple discrete elements rather than using a single capacitor, thereby improving filter precision while maintaining a modular and manageable structure.
Solution Approach 2:
The patent implements feedback connections where the output of the filter network is fed back to the input through controlled paths involving the history capacitors and switch network. This feedback mechanism allows the system to adjust and refine the filtering characteristics dynamically, enabling sharper passband-roll-off transitions and improved filtering efficiency without requiring a proportional increase in structural complexity.
2Manufacturing precision
If more capacitors and switch networks are added to improve filtering performance, then sharper transitions can be achieved, but power consumption increases
Solution Approach 1:
The filter network employs periodic switching operations controlled by clock signals, where the switch network alternates between connecting different history capacitors to the input and output nodes. This periodic action allows the system to achieve sharp filtering transitions through time-multiplexed capacitor connections rather than requiring all capacitors to be simultaneously active, thereby reducing average power consumption while maintaining high filter transition sharpness.
Solution Approach 2:
The history capacitors are periodically connected to and disconnected from the active filtering path. During each switching cycle, some capacitors are discarded from the current operation (disconnected) while others are recovered and prepared for the next cycle. This discarding and recovering mechanism reduces the number of capacitors that need to be simultaneously charged and discharged, thereby lowering power consumption while maintaining the sharp transition characteristics through the cascaded capacitor structure.
3Speed
If the cycling rate of sampling capacitor is increased to improve operational speed, then filtering speed increases, but power consumption and sensitivity to capacitor mismatches increase
Solution Approach 1:
The filter network segments the filtering function across multiple history capacitors in a cascaded arrangement, where each capacitor handles a portion of the filtering task. This segmentation reduces the burden on individual capacitors, allowing the system to operate at higher cycling rates without excessive power consumption. The distributed structure also reduces sensitivity to mismatches because the overall filter response is the cumulative effect of multiple capacitors rather than relying on a single critical capacitor value.
Solution Approach 2:
The patent utilizes parameter changes in the capacitor values and their interconnections to optimize the filter response at different cycling rates. By adjusting the capacitance values and the feedback coefficients in the switch network, the system can maintain stable filtering performance and reduced sensitivity to mismatches even when operating at higher speeds. This parameter optimization allows the filter to achieve high operational speed without proportionally increasing power consumption or mismatch sensitivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed filter network achieves improved filter characteristics with reduced power consumption, sharper transitions between passband and roll-off, and increased operational speed, while being fully reconfigurable and scalable, effectively addressing the limitations of existing technologies.
Implementation Method 1
a sampling capacitor or sampling capacitors CS which operate at a predetermined cycling rate to couple a sampling capacitor to at least one history capacitor CHi so as to share electrical charge between such selected history capacitor CHi and selected sampling capacitor CS
Implementation Method 2
the at least one sampling capacitor CS is subsequently flipped and connected back antiparallel so as to provide its charge with inverted polarity to the history capacitor CHi, wherein i=1
Data Source
AI summary
A discrete time filter network with an input signal connection and an output signal connection and comprising a capacitor bank with a plurality of history capacitors, and at least one sampling capacitor which operates at a predetermined cycling rate to couple to at least one history capacitor at a time, which history capacitor is selected from the capacitor bank so as to share electrical charge between such selected history capacitor and the sampling capacitor, wherein there is a plurality of sampling capacitors that are provided in the capacitor bank, and the discrete time filter network is provided with at least one switch network comprising a plurality of clock driven switches for making selected cyclical connections between the sampling capacitors and the history capacitors in the capacitor bank at the predetermined cycling rate.