Analog Neural Memory Decoders for Single-Cell Verify in VMM Arrays
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Solution Overview
Problem
Existing decoding circuits for conventional flash memory arrays are not suitable for use with vector-by-matrix multiplication (VMM) arrays in analog neuromorphic memory systems, as they fail to accommodate the verify operation on a single selected memory cell while performing a read operation on all memory cells in the array.
Innovation Solution
The development of specialized decoders, including word line drivers and bit line decoders, that enable individual programming, erasing, and reading of memory cells in a VMM array without disturbing other cells, and support continuous analog programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional flash memory decoding circuits are used, then the system can perform read operations on all memory cells, but it cannot perform verify operations on a single selected memory cell without disturbing other cells
Solution Approach 1:
The decoding circuit is segmented into separate word line decoding paths: a first decoding path for selecting a single word line during programming/erasing operations, and a second decoding path for selecting multiple word lines simultaneously during read operations. This segmentation allows the circuit to adapt to different operation modes while maintaining proper cell isolation through the use of separate decoding mechanisms for each operation type.
2Reliability
If specialized decoders are developed for VMM arrays, then individual programming and reading can be performed without disturbing other cells, but the device complexity increases
Solution Approach 1:
The decoding circuit is designed with multi-functionality to handle both conventional flash memory operations and analog neuromorphic VMM operations using a unified architecture. The same decoding circuit can perform single-cell programming, array-wide reading, and analog weight tuning operations, reducing overall system complexity despite the specialized requirements of VMM arrays.
Solution Approach 2:
The decoding circuit employs dynamic control mechanisms that adjust its behavior based on the operation mode. Control signals dynamically switch between different decoding paths and selection schemes, allowing the circuit to adapt its complexity level to match the specific operation being performed, thereby optimizing performance without permanently increasing hardware complexity.
3Use of energy by moving object
If separate multiplication logic circuits are eliminated, then energy consumption is reduced, but the difficulty of detecting and measuring synapse weights increases
Solution Approach 1:
The patent introduces intermediary sensing circuits and reference cell structures that facilitate the measurement of analog synapse weights stored in the crossbar array. These intermediary components act as mediators between the analog memory cells and the digital readout system, enabling accurate weight detection without requiring separate multiplication logic circuits, thus maintaining energy efficiency while solving the measurement challenge.
Data Source
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AI summary
Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.