Analog Neural Memory Output Circuit for Efficient Vector-Matrix Multiplication
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Solution Overview
Problem
Current artificial neural networks face challenges in achieving high-performance information processing due to a lack of adequate hardware technology, particularly in terms of energy efficiency and scalability, as they rely on bulky digital circuits for high connectivity between neurons.
Innovation Solution
The development of a hybrid output architecture for analog neural memory in deep learning artificial neural networks utilizing non-volatile memory arrays, which allows for continuous programming and individual tuning of memory cells, enabling precise weight adjustments and efficient vector-matrix multiplication operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If digital circuits are used for high connectivity between neurons, then connectivity is achieved, but energy efficiency deteriorates and device area increases
Solution Approach 1:
The patent replaces digital circuit-based neuron connectivity with analog crossbar array connectivity. The crossbar array uses analog voltage signals to represent weights and performs multiplication operations through Ohm's law, eliminating the need for digital multiplication circuits. This substitution of digital mechanics with analog physics achieves high connectivity while improving energy efficiency.
Solution Approach 2:
The crossbar array serves multiple functions simultaneously: it stores weights in memory cells, performs multiplication through conductance values, and sums results through parallel current paths. This multi-functionality eliminates the need for separate multiplication and addition logic circuits, reducing device area and improving energy efficiency while maintaining high connectivity.
2Adaptability or versatility
If digital circuits are used for high connectivity between neurons, then connectivity is achieved, but device area increases
Solution Approach 1:
The patent merges memory and computation functions into a single crossbar array structure. Memory cells are arranged in a compact grid where rows and columns form conductive paths, allowing simultaneous weight storage and multiplication operations. This merging eliminates the need for separate logic circuits, significantly reducing device area while maintaining high connectivity.
Solution Approach 2:
The patent replaces bulky digital logic circuits with compact analog crossbar structures. The crossbar array uses the physical properties of conductors and resistors to perform computation, eliminating the need for transistors and logic gates required in digital implementations. This substitution dramatically reduces device area while achieving high connectivity.
3Productivity
If separate multiplication and addition logic circuits are used, then computation is achieved, but device complexity increases
Solution Approach 1:
The crossbar array performs both multiplication and addition functions simultaneously. Multiplication is achieved through the conductance of memory cells (G = I/V), and addition occurs naturally through the parallel summation of currents at each output node. This multi-functionality eliminates the need for separate multiplication and addition logic circuits, reducing device complexity while maintaining computation capability.
Solution Approach 2:
The crossbar array performs computation passively using the physical properties of its components. The memory cells' conductance values automatically perform multiplication when voltage is applied, and the parallel circuit structure automatically sums the results. This self-service computation eliminates the need for active logic circuits, significantly reducing device complexity.
Data Source
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AI summary
Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives current from a W+ bit line and current from an associated W- bit line, and the output block generates an output signal that is a differential signal in certain embodiments and is a single ended signal in other embodiments.