Electric Analogue Stores TRIZ Cases

A dual regulation and feedback circuit keeps LED drive current stable during startup, preventing power-on overshoot and light source damage.

Surface plasmons in a grating Schottky diode extend silicon NIR detection beyond 1100 nm while preserving low-noise CMOS readout integration.

Reusable analog neural memory hardware adapts vector-by-matrix arrays and support circuits to different sizes, cutting custom design cost and time.

Sequential programming pulses deposit exact floating-gate charge in VMM memory cells, improving neural weight precision with lower time and energy cost.

Binary-search voltage regulation stabilizes charge pump output under process, supply, and load variation while supporting high-speed drive pulses.

Voltage-difference-triggered capacitor refresh maintains hysteresis accuracy, cuts power use, shortens testing, and protects regulators.

A sample-and-hold bias scheme shifts current mirror noise out of a narrow band, avoiding large capacitors and extra power draw.

A duty-cycled LDO and sample-and-hold circuit keeps reference voltage continuously available while conserving battery power.

A distributed tile current reference uses source degeneration and active biasing to hold accuracy while cutting power and area in cross-point memory.

Multiple voltage domains and staged buffers cut analog front-end loading while keeping ADC bandwidth, linearity, and speed stable under PVT variation.

AC grounding a reset node suppresses parasitic-capacitor distortion in a receiver buffer circuit, improving high-speed sampling accuracy.

Multiple voltage domains and staged buffers cut AFE loading and PVT sensitivity in high-speed time-interleaved ADC receivers.

A control circuit fixes sampled storage outputs after detection, producing a single glitch-free asynchronous output without arbitration.

Closed-loop pulse updates and ADC-based weight estimation improve analog memory programming accuracy for low-latency, low-energy edge AI.

Amplitude-controlled cancellation and complementary source following reduce clock feedthrough, memory effects, and distortion in high-speed SerDes sampling.

Separating sampling and holding into two amplifiers cuts input-output voltage error and improves sample-and-hold accuracy.

Parallel sample-and-hold modules with staggered clock phases cut spiky current, lowering power, settling error, and circuit area.

An auxiliary switch path extends tracking time in front-end sampling, helping ADC storage circuits follow high-frequency inputs with less distortion.

By coupling sampling directly to a latch, this circuit cuts two-stage delay and improves high-speed differential signal capture for SERDES and DDR.

A bootstrapped top-plate sampling scheme uses a voltage doubler and delayed inverted clocks to cut distortion and widen ADC bandwidth.

A boosted-impedance bootstrap circuit keeps sampling-switch gate voltage stable to preserve ADC DC level and signal swing.

Adjustable timing across parallel sample-and-hold branches raises LiDAR sampling resolution without relying on high-speed ADCs.

By converting input voltage to current, this track-and-hold circuit avoids bootstrapping and level-shifted clocks to improve speed, linearity, and memory error control.

Timing patterns on a serial interface are converted into configuration codes, letting a signal-processing circuit select modes without extra pins.

A bootstrap gate boost keeps ADC switch ON-resistance low across input voltage swings, improving sample-and-hold accuracy and noise tolerance.

Multiple dedicated input buffers preserve sampling bandwidth, while power gating shuts down idle buffers to cut energy use in high-frequency sampling.

A hybrid analog output circuit uses W+ and W- bit-line currents to enable precise weight tuning and energy-efficient vector-matrix multiplication.

Cross-coupled dummy transistors cut parasitic capacitance and clock feed-through in sample-and-hold circuits for faster, cleaner ADC sampling.

Split sampling capacitors and separate NMOS/PMOS biasing extend sample-and-hold output swing while improving SNR and lowering power.

A phased sensing scheme records prior node charges and samples transit points to improve read margin and speed in low-voltage non-volatile memory.

Adjustable current-cell ramp generation adapts the ToF A/D range to light conditions, improving depth accuracy while preventing DC offset.

A parallel DFE and offset compensation path cuts LPDDR intersymbol interference while limiting receiver power use.

A bias voltage generation circuit tracks output voltage to cut off-mode T-switch leakage and preserve ADC conversion accuracy.

A boosted-impedance bootstrap circuit keeps sampling-switch gate voltage stable while preserving DC level and input resistance in ADCs.

Differential capacitive sensing detects switching-node signals accurately in high-voltage circuits while limiting parasitic capacitance and offset errors.

Multiple MOSFET switches and a native transistor cut S/H leakage, extend hold time, and lower low-power sampling demand.

A capacitive differential sensing scheme cuts charge sharing and leakage between memory cells and sense circuitry while improving read speed and signal detection.

Parallel decision feedback equalization and offset compensation reduce LPDDR intersymbol interference without raising power use.

Balanced ternary weights and selective bit-line charge paths cut cell-current variation while keeping in-memory MACs energy efficient.

Voltage sampling on an integration capacitor reveals RC time constants where direct line measurement is unavailable, enabling RC delay compensation.

Two parallel sampling units and a shared holding stage cut circuit complexity, save board space, and improve signal-to-noise ratio.

Alternating capacitor charging and discharging suppresses leakage current and sinusoidal noise to keep frequency-voltage output stable.

A parallel decision feedback equalization path cuts LPDDR intersymbol interference and channel-loss effects without raising receiver power.

A common sampling circuit mixes the analog input with a test signal to calibrate sub-ADC gain and offset mismatches during normal operation.

Pairing capacitive DACs to set and balance sampler thresholds cuts offset, quantization error, and noise in high-speed serial links.

Configurable parallel sample-and-hold branches use adaptable time delays to raise LiDAR sampling resolution without cutting frame rate.

Multiple-timing amplitude sampling speeds equalizer adaptation for ISI compensation while preserving waveform accuracy in wired communication circuits.

AGMI input grouping and CVSS voltage stacking cut CIM latency, improve signal margin, and lower energy use for precise multi-bit MAC.

A two-stage LPDDR sampling circuit integrates decision feedback and offset compensation to cut intersymbol interference without added power.

Phase-offset reception and transmission clocks create programmable analog delay with low latency, lower power, and wide-band readout.

A cascode-assisted source follower uses complementary output control to cancel non-linear currents and cut HD3 in low-voltage ADC buffers.

A transformer-coupled bootstrap keeps switch gate-source voltage stable at high sampling rates, reducing distortion in wide-swing ADC inputs.

A third-capacitor ADC scheme keeps touch sensing in range for accurate position capture with lower power in secure smart card interfaces.

Balanced ternary weights and selective conductive paths enable denser in-memory multiplication with higher throughput and lower energy use.

Cascaded MOSFET switches and a native transistor cut leakage in sample-and-hold circuits, extending analog hold time and reducing low-power resampling.

Two parallel sampling paths with opposite-phase clocks double sampling rate while cutting power use and easing timing margin.

Switchable differential inputs isolate external and internal noise sources, improving weak-signal optical print recognition in mobile devices.

Offset voltages are sampled into parasitic capacitors for cancellation during sensing, increasing margin in low-voltage semiconductor reads.

Multiple switched-capacitor groups suppress second-order nonlinearity and adjust output common-mode voltage with lower ADC power use.

Selectable sub-ADCs match sampling capacity to signaling speed, improving data recovery accuracy while avoiding unnecessary power and complexity.

Pre-biasing the sampling transistor backgate before sampling cuts leakage current, preserves capacitor charge, and avoids larger capacitors.

A sample-and-hold plus reference voltage path cancels common-mode perturbations to stabilize gain and improve SNDR in charge-steering amplifiers.

Biasing the MOS switch source and substrate by state cuts hold-mode leakage while preserving fast capacitor charging and voltage stability.

A track-and-hold feedback network masks startup voltage dip in switched capacitor charging, cutting amplifier power, area, and complexity.

Compensation circuitry uses tunneling regions and storage capacitors to offset floating-gate charge loss and preserve analog accuracy over time.

A native MOS buffer keeps sample-and-hold output near 1.0-1.2V, reducing level-shifting noise and distortion in low-voltage ADCs.

Two amplifiers split boost-switch impedance control and signal sampling to cut sample-and-hold power use while preserving linearity.

Preloads MRAM with temporary error correcting data to recover from thermal errors during reflow soldering, avoiding increased switching current.

Dynamic bit-line charging configurations balance read accuracy and speed by selecting schemes based on operational conditions.