Multi-Voltage ADC Data Path for PVT-Stable High Sampling Rates
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Solution Overview
Problem
As ADC sampling rates increase, time-interleaved ADCs become larger in implementation area, leading to increased loading of the analog front-end of receivers, and are sensitive to process, voltage, and temperature variations, affecting performance and power consumption.
Innovation Solution
A data path configuration using multiple voltage domains (VddH, VddM, VddL) for the AFE, THA, and TI-ADC, with PMOS and NMOS buffers, minimizing PVT variations and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ADC sampling rate is increased, then data rate and signal-to-noise ratio are improved, but implementation area and loading on analog front-end increase
Solution Approach 1:
The ADC is divided into multiple parallel channels (e.g., 4 channels) that operate at lower individual sampling rates. Each channel processes a portion of the data, and their outputs are interleaved to achieve the high overall data rate without requiring a single large high-speed converter, thus reducing total implementation area.
Solution Approach 2:
The patent transitions from a single-channel time-domain approach to a multi-channel time-interleaved approach. By adding the channel dimension, the system achieves high data rates through parallel processing rather than increasing the speed of a single converter, effectively moving the problem into a higher dimensional solution space.
2Productivity
If ADC sampling rate is increased, then data rate is improved, but loading on analog front-end increases
Solution Approach 1:
The analog front-end loading is segmented across multiple parallel ADC channels, each operating at a manageable sampling rate. This distributes the power consumption and loading requirements across several lower-power channels rather than concentrating it in a single high-power channel.
Solution Approach 2:
The system dynamically switches between different voltage domains (VddH, VddM, VddL) for different circuit blocks based on their specific requirements. This dynamic voltage scaling optimizes power consumption by applying appropriate voltage levels to each component rather than using a uniform high voltage across the entire system.
3Use of energy by stationary object
If multiple voltage domains are used, then power consumption is optimized, but device complexity increases
Solution Approach 1:
Different voltage domains (VddH, VddM, VddL) are applied to different circuit blocks based on their specific performance and power requirements. High-voltage domains are used where high performance is critical, while low-voltage domains are used where power savings are prioritized, creating local optimization throughout the system.
Solution Approach 2:
Buffer circuits are introduced as intermediary components between different voltage domains to enable signal transmission across voltage boundaries. These buffers act as mediators that translate signals between different voltage levels, allowing the multi-voltage architecture to function coherently despite the complexity of interfacing different domains.
Data Source
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AI summary
An example data path (17) to a receiver (14) includes: an analog front-end circuit (AFE) (16) configured to receive a first voltage supply; a first circuit (18) coupled to an output of the AFE (16), the first circuit (18) including: a first buffer having an input coupled to the output of the AFE (16); a second buffer; a first switch coupled between an output of the first buffer and an input of the second buffer; and a second switch coupled between an output of the second buffer and an input of an ADC (20) of the receiver (14); wherein the first buffer is configured to receive the first voltage supply, the second buffer is configured to receive a second voltage supply, and the ADC (20) is configured to receive a third voltage supply less than the first voltage supply.