Analog Memory Cell Readout Using Dynamic Bit-Line Charging
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Solution Overview
Problem
Existing memory devices face a trade-off between read accuracy and speed, with highly accurate read operations being slow and fast read operations having reduced accuracy, limiting overall data retrieval speed, especially in scenarios where lower accuracy is sufficient.
Innovation Solution
Implementing multiple readout schemes with different bit-line charging configurations and sense times, allowing for the selection of a scheme based on the specific read operation condition, such as the age of memory cells or the purpose of the read operation, to balance accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single readout scheme with long sense time is used to ensure high accuracy, then read accuracy is improved, but readout speed deteriorates
Solution Approach 1:
The patent implements dynamic selection between multiple readout schemes based on actual read operation conditions. The system transitions from a static single-readout approach to a dynamic multi-scheme selection approach, where the sense time and charging configuration are adjusted according to the specific requirements of each read operation, thereby optimizing the balance between accuracy and speed.
Solution Approach 2:
The patent changes the parameter of sense time by implementing multiple readout schemes with different sense times. The system can select from a first readout scheme with a first sense time (longer, higher accuracy) and a second readout scheme with a second sense time (shorter, faster), allowing parameter adjustment based on operational conditions to resolve the accuracy-speed trade-off.
2Speed
If a single readout scheme with fast charging is used to increase readout speed, then readout speed is improved, but read accuracy deteriorates
Solution Approach 1:
The system dynamically adapts the readout scheme selection based on the specific conditions of each read operation. Rather than using a fixed fast-reading approach that compromises accuracy, the system can switch between fast and accurate reading modes depending on the operational context, thereby maintaining high readout speed while preserving accuracy when needed.
Solution Approach 2:
The patent adjusts the charging rate parameter by implementing different bit-line charging configurations. The system can use a first charging rate for high-speed readout when accuracy requirements are low, and a second charging rate for high-accuracy readout when speed requirements are relaxed, thus resolving the contradiction between speed and accuracy through parameter variation.
3Productivity
If multiple readout schemes are implemented to balance accuracy and speed, then average readout speed is improved, but device complexity increases
Solution Approach 1:
The patent segments the readout operation into distinct schemes (first readout scheme with first sense time, second readout scheme with second sense time), each optimized for specific conditions. This segmentation allows the system to select the appropriate scheme based on operational requirements, improving average readout speed by matching the right scheme to the right condition while keeping the complexity manageable through clear differentiation of schemes.
Solution Approach 2:
The system implements a universal readout mechanism that can perform multiple functions (high-speed reading, high-accuracy reading) using a unified framework of multiple schemes. The controller is designed to evaluate conditions and select appropriate schemes, making the complexity management systematic and allowing the same hardware to serve multiple reading purposes efficiently.
Data Source
AI summary
A method for data storage includes providing at least first and second readout schemes for reading storage values from a group of analog memory cells that are connected to respective bit lines. The first readout scheme reads the storage values using a first bit line charging configuration having a first sense time, and the second readout scheme reads the storage values using a second bit line charging configuration having a second sense time, shorter than the first sense time. A condition is evaluated with respect to a read operation that is to be performed over a group of the memory cells. One of the first and second readout schemes is selected responsively to the evaluated condition. The storage values are read from the group of the memory cells using the selected readout scheme.