Sample-and-Hold Timing for High-Rate LiDAR Distance Sampling

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Solution Overview

Problem

Existing LIDAR systems face challenges in achieving high sample rates without significantly reducing frame rates or increasing system complexity and cost, as they rely on non-configurable sample-and-hold arrays and require multiple data sets with slight time offsets to achieve accurate distance measurements.

Innovation Solution

A configurable sample-and-hold circuit with parallel branches and a clock and timing circuit that allows adaptable time delays and sampling phases, enabling sampling with different resolutions and frequencies, and a digital processing block for averaging samples.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple data sets with slight time offsets are collected to achieve high sample rate, then measurement precision is improved, but frame rate is reduced by a factor of N

Engineering Contradiction:

Improvedistance measurement accuracyVSAvoidframe rate

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The sample-and-hold array is divided into N segments or channels, each capable of independent sampling. By configuring different time delays for each segment, the system can collect multiple samples simultaneously in parallel rather than sequentially, maintaining high effective sample rate while preserving frame rate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system introduces configurable and adaptable time delays for each sample-and-hold block, allowing dynamic adjustment of sampling timing. This enables the system to optimize between high sample rate and high frame rate based on measurement requirements, rather than being fixed in a single operating mode.

Inventive Principle:

Principle #15Dynamics

2Measurement precision

If multiple data sets with slight time offsets are collected to achieve high sample rate, then measurement precision is improved, but device complexity is increased

Engineering Contradiction:

Improvedistance measurement accuracyVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The sample-and-hold circuit is designed as a configurable and adaptable system that can perform multiple functions: it can operate in high sample rate mode, high frame rate mode, or any intermediate configuration. The same hardware structure serves multiple purposes by adjusting time delay parameters, reducing the need for separate dedicated circuits for different operating modes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Device complexity

If non-configurable sample and hold array is used, then device complexity is reduced, but adaptability is limited

Engineering Contradiction:

Improvesystem complexityVSAvoidsampling configuration flexibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS11430533B2Sample-and-hold circuit arranged for setting an adaptable time delay

Publication Date: 2022.08.30 MELEXIS TECH NV

AI summary

A sample-and-hold circuit is provided that includes a plurality of sample-and-hold branches arranged in parallel and each including a buffer and a sample-and-hold block including one or more sample-and-hold cells. The sample-and-hold circuit further includes a clock and timing circuit arranged for setting an adaptable time delay to enable sampling and sampling phase for each sample-and-hold block. The time delay of at least one sample-and-hold block can be set to value bigger than one sampling clock period.