Source Follower Cascode Cancellation for Low-Voltage HD3 Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Source follower circuits in semiconductor devices experience increased third harmonic distortion (HD3) due to limited drain-source voltage and drain-source conductance non-linearity, especially at lower power supply voltages and large input signal swings, which limits the performance of analog-to-digital converters (ADCs).
Innovation Solution
The implementation of a source follower circuit with a cascode transistor and a switched capacitor attenuator that compensates for non-linearity by using a complementary signal to control the cascode transistor, optimizing the attenuation factor to reduce HD3, and incorporating a feed forward capacitor to improve high-frequency conductance non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a source follower circuit is used with lower power supply voltages and large input signal swings, then the buffer can operate with wider voltage range and higher signal dynamic range, but third harmonic distortion increases due to limited drain-source voltage and drain-source conductance non-linearity
Solution Approach 1:
The source follower circuit is segmented into multiple transistors (first source follower transistor, second source follower transistor, cascode transistor) with distinct functional roles. The cascode transistor is separated to handle the non-linear current component, allowing the main input transistor to maintain linearity while operating with lower power supply voltages and large signal swings.
Solution Approach 2:
A cascode transistor is introduced as an intermediary element between the input transistor and the load. This cascode transistor acts as a mediator that carries the non-linear current component, thereby protecting the input transistor from operating in its non-linear region and maintaining overall circuit linearity even under large signal swings and lower supply voltages.
2Device complexity
If the drain-source conductance non-linearity is present in the input transistor, then the circuit structure remains simple, but third harmonic distortion increases
Solution Approach 1:
The circuit segments the current path into linear and non-linear components. The input transistor handles the linear signal transmission, while the cascode transistor is specifically assigned to carry the non-linear current component, thereby eliminating third harmonic distortion without significantly increasing overall circuit complexity.
Solution Approach 2:
The non-linear current component is extracted from the main signal path by using the cascode transistor. This extracted non-linear current is then diverted through the cascode device, leaving the main input transistor to operate in its linear region, thus removing the source of third harmonic distortion while maintaining circuit simplicity.
3Manufacturing precision
If a cascode transistor is added to compensate for non-linearity, then third harmonic distortion is reduced, but device complexity increases
Solution Approach 1:
The cascode transistor serves multiple functions simultaneously: it compensates for non-linearity by carrying the non-linear current component, it provides impedance transformation, and it maintains the linear operation of the input transistor. This multi-functionality reduces the need for additional compensation circuits, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The invention changes the operating parameters of the transistors by introducing the cascode configuration. The cascode transistor modifies the drain-source voltage distribution, allowing the input transistor to operate with optimized voltage and current parameters that minimize non-linearity, thus reducing third harmonic distortion with minimal additional complexity.
Data Source
AI summary
A buffer circuit includes a first differential signal input, a second differential signal input, a first source follower circuit, and a second source follower circuit. The first source follower circuit includes a first signal output, and a first input transistor. The first input transistor is coupled to the first differential signal input, and is configured to drive the first signal output. The second source follower circuit includes a second signal output, a second input transistor, and a cascode transistor. The second input transistor is coupled to the second differential signal input, and is configured to drive the second signal output. The cascode transistor is coupled to the second input transistor and the first signal output, and is configured to compensate for non-linearity of the second input transistor based on an output signal provided at the first signal output.