Backgate-Biased Sampling Switch for Low Leakage Hold Circuits
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Solution Overview
Problem
Low leakage switches in sample and hold systems face significant leakage currents, especially at elevated temperatures, which affect charge preservation on sampling capacitors, and existing solutions either increase capacitor size or power consumption.
Innovation Solution
A low leakage switch design incorporating a pre-sampling stage with a pre-sampling capacitor and transistor, along with a specific switching scheme and differential amplifiers, minimizes leakage currents by adjusting voltage levels and stabilizing backgate voltages, reducing channel leakage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitance value of the sampling capacitor is increased to overcome leakage current effects, then charge preservation is improved, but chip area and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-charging the sampling capacitor through a pre-charge transistor before the main sampling operation. This pre-charging action prepares the capacitor with the correct voltage level, reducing the impact of leakage currents during the hold phase without requiring increased capacitance value, thereby avoiding additional chip area.
2Reliability
If the capacitance value of the sampling capacitor is increased to overcome leakage current effects, then charge preservation is improved, but power consumption increases
Solution Approach 1:
The pre-charge transistor performs preliminary action by charging the sampling capacitor to the correct voltage level before sampling. This eliminates the need for larger capacitors that would consume more power, thereby reducing overall power consumption while maintaining charge preservation.
3Object-generated harmful factors
If backgate voltage is controlled to reverse bias backgate diodes, then leakage current is reduced, but minimum saturation current still flows through the diodes
Solution Approach 1:
The patent uses preliminary action by pre-charging backgate voltage sampling capacitors through dedicated transistors before the main sampling operation. This pre-charging action establishes the correct backgate voltage levels that reverse bias the backgate diodes, reducing leakage current while maintaining voltage stability during the hold phase.
Solution Approach 2:
The patent introduces intermediary elements (backgate voltage sampling capacitors and control transistors) that mediate between the input voltage and the backgate terminals. These intermediaries allow precise control of backgate voltage to achieve reverse biasing of diodes, reducing leakage current while maintaining stability.
4Object-generated harmful factors
If a cascade of transistors with backgate voltage sampling is used, then leakage current is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the switch circuit into multiple independent transistor stages, each with its own backgate voltage sampling capacitor. This segmentation allows each transistor to be independently optimized for low leakage while maintaining overall circuit functionality, managing complexity through modular design.
Solution Approach 2:
The patent introduces intermediary backgate voltage sampling capacitors and control transistors that act as mediators between the input signal and the transistor backgates. These intermediaries enable precise control of leakage current through each stage while maintaining a structured, manageable circuit architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage currents and voltage errors on sampling capacitors, allowing for longer hold times with reduced power consumption and improved charge preservation.
Implementation Method 1
a pre-sampling capacitor (CSI) coupled with one side to an input node (IN)
Implementation Method 2
backgate voltage sampling capacitors (CSB1, CSB2) coupled to backgates (BG1, BG2) of the transistors
Implementation Method 3
a decoupling transistor (PISO) coupled with its channel between the backgate of the first transistor and a node (VBG1)
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
The invention relates to a low leakage switch having an input node for receiving an input voltage and an output node for providing an output voltage. The low leakage switch comprises a main sampling transistor the backgate voltage of which is biased through other transistors, and wherein the control gate of the main sampling transistor is controlled through a second control signal and the control gates of the other transistors are controlled through a first control signal, wherein the electronic device is further configured to activate the other transistor for adjusting the backgate voltage of the main sampling transistor through the first control signal before activating the main sampling transistor for sampling the input voltage on a main sampling capacitor through the second control signal.