Current-Mode Track-and-Hold Circuit for Fast Linear Sampling
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Solution Overview
Problem
Sample-and-hold circuits in high-speed applications face limitations in linearity and dynamic range due to the need for bootstrapping and level-shifted clocks, which restrict conversion speeds and introduce memory errors.
Innovation Solution
A sample-and-hold circuit design that converts input voltage to current, eliminating the need for bootstrapping and level-shifted clocks, and incorporates feedforward compensation and discharge circuits to reduce memory errors and enhance bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bootstrapping technique is used to sample input voltage, then linearity is improved, but conversion speed is limited due to initial charging delay and tracking phase
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage-mode bootstrapping to current-mode operation. By converting the input voltage to current through resistors and operating the transistors in current mode, the circuit eliminates the bootstrapping charging delay while maintaining linearity through controlled current flow through the transistor channels.
Solution Approach 2:
The patent substitutes the voltage-based bootstrapping mechanism with a current-based direct sampling mechanism. Instead of using voltage control and capacitive charging (voltage-mode), the system uses current flow through resistors and transistors (current-mode) to achieve sampling, thereby eliminating the inherent speed limitations of voltage-mode bootstrapping.
2Measurement precision
If bootstrapping is applied to transistor switch, then minimal distortion is achieved, but additional transistors and capacitor are required increasing circuit complexity
Solution Approach 1:
The patent extracts and eliminates the bootstrapping capacitor and associated voltage control circuitry from the sampling circuit. By transitioning to current-mode operation where current flows directly through the transistor channels controlled by differential voltages, the circuit achieves minimal distortion without requiring the additional capacitive elements and complex voltage control networks of bootstrapping.
Solution Approach 2:
The patent makes the transistor channels serve multiple functions: they act as both the sampling switches and the signal transmission paths. The differential pair transistors simultaneously perform switching, signal routing, and linear signal transmission, eliminating the need for separate bootstrapping circuitry and reducing overall circuit complexity.
3Productivity
If higher conversion speeds are achieved, then productivity is improved, but memory errors increase due to reduced sampling and processing time
Solution Approach 1:
The patent applies preliminary action by establishing the current flow path and transistor operating states before the actual sampling event. The differential pair is pre-biased and ready, with current already flowing through the resistors, so that when the sampling signal arrives, the transistors are immediately in the correct state to accurately track and hold the input current without memory errors from previous states.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed operation with improved linearity and dynamic range by avoiding bootstrapping and level-shifted clocks, while reducing memory errors through effective discharge mechanisms, thus enhancing the overall performance of the sample-and-hold circuit.
Implementation Method 1
first and second transistors coupled in series between the second terminals of the first and second input resistors
Implementation Method 2
third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors
Data Source
AI summary
An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. A first capacitor is coupled between the first and second transistors and a second capacitor is coupled between the third and fourth transistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.