Time-Interleaved Sampling Circuit with Power-Gated Input Buffers

The patent divides the single input buffer into multiple separate input buffers, with each sampling unit having its own dedicated input buffer. This segmentation eliminates the distribution network between a single buffer and multiple sampling units, thereby removing the bandwidth limitation caused by the resistance and capacitance of the distribution network. Each sampling unit independently receives the input signal through its own buffer, ensuring high sampling bandwidth without requiring a complex distribution network.

The patent implements dynamic power management by introducing power gating switches that can selectively power down individual input buffers when they are not needed. This allows the circuit to adapt its power consumption based on the actual sampling requirements. When a sampling unit is inactive, its associated input buffer can be powered down, reducing overall power consumption while maintaining the capability for high bandwidth operation when needed.

The power gating switches serve multiple functions: they act as power-down control elements to reduce power consumption, and simultaneously function as part of the signal path control mechanism. The same clock signals that control the sampling operation also control the power gating switches, eliminating the need for separate control circuitry. This multi-functionality reduces the overall complexity increase that would otherwise result from adding power management components.