Parallel Track-and-Hold Circuit for High Sampling at Lower Power
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Solution Overview
Problem
In master-slave track-and-hold circuits, achieving a high sampling rate requires a high clock frequency, leading to increased power consumption and reduced timing margin.
Innovation Solution
A track-and-hold circuit with two sampling circuits connected in parallel, receiving in-phase data signals and clock signals with opposite phases, and a multiplexer to select and output data from the hold mode, while sharing current sources between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high clock frequency is used to achieve a high sampling rate in a master-slave track-and-hold circuit, then the sampling rate is improved, but the power consumption increases
Solution Approach 1:
The circuit is divided into two parallel sampling circuits that operate on alternating clock cycles. Each sampling circuit processes one half of the sampling rate, allowing the overall system to achieve double the sampling rate of a single circuit while maintaining lower power consumption per circuit.
Solution Approach 2:
The two sampling circuits operate periodically with opposite-phase clock signals, where one circuit is active during one clock cycle and the other circuit is active during the next clock cycle. This periodic alternation enables high sampling rates while distributing power consumption over time.
2Productivity
If a high clock frequency is used to achieve a high sampling rate in a master-slave track-and-hold circuit, then the sampling rate is improved, but the timing margin decreases
Solution Approach 1:
By segmenting the sampling function into two parallel circuits operating on alternating cycles, each circuit operates at a lower effective frequency, thereby increasing the timing margin for each individual sampling operation while achieving a high overall sampling rate.
3Productivity
If two separate current sources are used for two sampling circuits, then each circuit has sufficient current supply, but the power consumption increases
Solution Approach 1:
Two sampling circuits share a common current source instead of each having a dedicated current source. This merging of the current supply function reduces the total power consumption while both circuits can still operate simultaneously on alternating cycles.
Solution Approach 2:
The single current source is designed to serve multiple functions by supplying current to either of the two sampling circuits depending on which one is active during a given clock cycle, thereby reducing overall power consumption.
Data Source
AI summary
A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.