Native MOS Sample-and-Hold Buffer for Low-Voltage Noise Reduction
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Solution Overview
Problem
Low voltage integrated circuits, particularly in high resolution pipelined analog-digital converters, face significant noise issues due to level shifting in sample-and-hold amplifiers, which affects signal-to-noise plus distortion ratio (SNDR) performance, as existing technologies struggle to maintain optimal voltage levels for proper operation.
Innovation Solution
A sample-and-hold amplifier design incorporating a buffer circuit with a native MOS transistor, where the threshold voltage is substantially close to 0V, coupled between a supply voltage source and ground, effectively mitigates level shifting effects by maintaining appropriate output signal voltage levels within the range of 1.0V to 1.2V, ensuring proper operation of subsequent circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional sample-and-hold amplifier is used in low voltage applications, then the circuit can operate at low voltage, but level shifting noise occurs and SNDR performance deteriorates
Solution Approach 1:
The patent changes the threshold voltage parameter of the MOS transistor to substantially 0V (from conventional non-zero values). This parameter change allows the transistor to operate without level shifting effects, eliminating noise while maintaining low voltage operation. The supply voltage is specifically set between 1.0V to 1.2V to optimize this operation.
2Use of energy by moving object
If the supply voltage is reduced to low levels, then power consumption decreases, but the output voltage level becomes insufficient for proper operation of subsequent circuits
Solution Approach 1:
The patent changes the threshold voltage parameter to substantially 0V, which eliminates level shifting in the output signal. This ensures that the output voltage remains at the correct level (within 1.0V to 1.2V range) even when operating from low supply voltage, ensuring proper operation of subsequent circuits while maintaining low power consumption.
3Power
If a sample-and-hold amplifier with non-zero threshold voltage transistor is used, then the transistor can provide voltage gain, but level shifting occurs and noise increases
Solution Approach 1:
The patent changes the threshold voltage parameter to substantially 0V, which eliminates level shifting noise while maintaining the transistor's ability to provide voltage gain. The transistor operates in the linear region with this threshold voltage setting, enabling it to function as an effective voltage amplifier without introducing level shifting artifacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces noise and distortion in low voltage applications, maintaining optimal voltage levels for the sample-and-hold amplifier output, thereby enhancing the SNDR performance and ensuring normal operation of subsequent circuits.
Implementation Method 1
a native MOS transistor coupled to the output node. In some embodiments, a threshold voltage of the native MOS transistor is substantially closer to 0V or equal to 0V
Data Source
AI summary
A sample-and-hold amplifier is provided. The sample-and-hold amplifier comprises a sample-and-hold circuit and a buffer circuit. The sample-and-hold circuit receives an input signal and transmits the input signal to a first node according to a control signal. The buffer circuit is coupled between a supply voltage source and a ground and controlled by the first node to provide an output signal at an output node. The buffer circuit comprises a native MOS transistor coupled to the output node.