Asynchronous Signal Sampling Circuit for Glitch-Free Output
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Solution Overview
Problem
Asynchronous logic circuits are susceptible to glitches causing errors like metastability and race conditions, particularly due to external input signal transients, and existing solutions are complex and time-consuming, producing multiple output signals that require additional arbitration.
Innovation Solution
A simplified asynchronous circuit design using storage elements (latches or flip-flops) to generate a single sanitized output signal by fixing storage outputs upon detection of a sample, with a control circuit generating a sample ready signal to indicate output readiness, reducing complexity and preventing glitches from propagating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex circuit designs with multiple sampling elements and arbitration logic are used to sanitize glitchy input signals, then reliability is improved by preventing glitches from propagating, but device complexity increases and sampling time increases
Solution Approach 1:
The patent extracts the essential sampling function from complex arbitration logic by using a single sampling element that directly captures the input signal state. The storage element isolates the sampled value from subsequent glitches, eliminating the need for multiple sampling elements and complex arbitration circuits while maintaining glitch-free output.
Solution Approach 2:
The storage element is configured to capture and hold the input signal state at the moment of sampling, performing the sanitization action in advance before glitches can propagate downstream. This preliminary capture prevents subsequent glitchy transitions from affecting the output, achieving reliability with simpler circuitry.
2Reliability
If complex logic elements and multiple logical loops are used in sampling circuits, then reliability is improved by ensuring stable outputs, but productivity decreases due to longer sampling times
Solution Approach 1:
The patent removes unnecessary logical loops and complex arbitration logic from the sampling path. A single sampling element feeds directly to a storage element, creating a streamlined path that captures the signal state quickly without the time-consuming iterative arbitration processes found in complex designs, thereby improving sampling speed while maintaining stability.
Solution Approach 2:
The storage element performs the stabilization function immediately upon receiving the sampled signal, holding the valid state ready for output before any potential glitches occur. This preliminary stabilization eliminates the need for multiple logical loops to verify stability, reducing sampling time while ensuring reliable stable outputs.
3Reliability
If multiple separate output signals are generated from sampling elements, then reliability is improved by providing stable sampled values, but device complexity increases due to additional arbitration circuitry needed to combine outputs
Solution Approach 1:
The patent extracts only the essential sampled value from the input signal using a single sampling element, eliminating the generation of multiple separate output signals. The storage element then holds this single sampled value, removing the need for arbitration circuitry to combine multiple outputs while maintaining reliable stable sampling.
Solution Approach 2:
The storage element captures and holds the sampled signal state in advance, preparing a single stable output value before it is needed downstream. This preliminary preparation of a single stable value eliminates the subsequent need for arbitration logic to resolve multiple outputs, reducing circuit complexity while ensuring reliability.
Data Source
AI summary
An asynchronous circuit portion for sampling an input signal is provided. The asynchronous circuit portion comprises a sampling circuit portion arranged to receive the input signal and to generate first and second sample signals; a first storage element arranged to generate a first storage signal on a first storage output on reception of the first sample signal; and a second storage element arranged to generate a second storage signal on a second storage output on reception of the second sample signal. A control circuit portion is arranged to detect if either of said first and second storage signals has been generated, to fix the first and second storage outputs and to generate a sample ready signal. The circuit portion generates an output signal corresponding to the input signal using the first storage output when the sample ready signal is generated.