Top-Plate Sample-and-Hold Circuit for High-Linearity ADC Sampling
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving high-speed and high-resolution sampling while maintaining linearity over a wide frequency range, especially in 5G and millimeter wave applications, due to limitations in clock signal generation and sampling methods.
Innovation Solution
The proposed solution involves a sample and hold circuit with a voltage doubler circuit and transistors configured to provide a clock signal with specific voltage levels, using a delayed and inverted clock scheme to enable top-plate bootstrapped sampling, which overcomes the drawbacks of bottom-plate sampling and achieves higher speed, bandwidth, and integration with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bottom-plate sampling is used in ADC, then the circuit can be implemented, but it suffers from distortion and limited linearity over frequency range
Solution Approach 1:
The patent inverts the conventional bottom-plate sampling approach by implementing top-plate sampling, where the sampling switch is connected to the top plate of the capacitor rather than the bottom plate. This inversion fundamentally changes the sampling mechanism to eliminate the distortion and linearity limitations inherent in bottom-plate sampling, achieving superior performance across a wide frequency range.
2Speed
If high-speed sampling is implemented in ADC, then bandwidth increases, but power consumption increases and linearity degrades
Solution Approach 1:
The patent changes the voltage level parameter of the clock signal by implementing a voltage doubler circuit that generates clock signals at twice the supply voltage (2VDD). This parameter change enables the top-plate sampling switches to operate at higher voltage levels, allowing for faster switching speeds and higher bandwidth while maintaining power efficiency through the specific circuit configuration and timing control.
3Speed
If clock signal voltage level is increased to improve sampling speed, then bandwidth increases, but the clock signal exceeds power node voltage levels causing circuit limitations
Solution Approach 1:
The patent introduces a voltage doubler circuit as an intermediary component that generates the high-voltage clock signals (2VDD) needed for fast top-plate sampling. This intermediary circuit resolves the conflict between needing high voltage for fast switching and the constraint that clock signals must exceed power node levels, by providing the necessary voltage boost without directly connecting to the power nodes in a way that would cause circuit limitations.
4Measurement precision
If top-plate bootstrapped sampling is implemented, then linearity and bandwidth improve, but additional circuit components are required
Solution Approach 1:
The patent merges multiple functions into the top-plate sampling circuit architecture. The same circuit structure that enables top-plate sampling also provides the bootstrapped voltage generation, the sampling switch control, and the capacitor charging/discharging mechanisms. By combining these functions into a unified top-plate architecture rather than separate bottom-plate components, the patent achieves improved linearity and bandwidth while managing circuit complexity through functional integration.
Data Source
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AI summary
Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.